Program Interference in MLC NAND Flash Memory Characterization

Program Interference in MLC NAND Flash Memory: Characterization, Modeling, and Mitigation Yu Cai 1 Onur Mutlu 1 Erich F. Haratsch 2 Ken Mai 1 Carnegie Mellon University 2 LSI Corporation 1

Flash Challenges: Reliability and Endurance § P/E cycles (provided) A few thousand § P/E cycles (required) Writing the full capacity of the drive 10 times per day for 5 years (STEC) E. Grochowski et al. , “Future technology challenges for NAND flash and HDD products”, Flash Memory Summit 2012 > 50 k P/E cycles 2

NAND Flash Memory is Increasingly Noisy Write Noisy NAND Read 3

Future NAND Flash-based Storage Architecture Noisy Memory Signal Processing Raw Bit Error Rate Lower High Error Correction Uncorrectable BER < 10 -15 Our Goals: Model NAND Flash as a digital communication channel Design efficient reliability mechanisms based on the model 4

NAND Flash Channel Model Write (Tx Information) Noisy NAND Read (Rx Information) Simplified NAND Flash channel model based on dominant errors Write Additive White Gaussian Noise § Erase operation § Program page operation Cell-to-Cell Interference § Neighbor page program Cai et al. , “Threshold voltage distribution in MLC NAND Flash Memory: Characterization, Analysis, and Modeling”, DATE 2013 ? Time Variant Retention Read § Retention Cai et al. , “Flash Correct-and-Refresh: Retentio aware error management for increased flash memory lifetime”, ICCD 2012 5

Outline n n Background on Program Interference Characterization of Program Interference Modeling and Predicting Program Interference Mitigation of Program Interference q n Read Reference Voltage Prediction Conclusions 6

How Current Flash Cells are n. Programmed Programming 2 -bit MLC NAND flash memory in two steps ER (11) 0 0 ER (11) LSB Program Temp (0 x) ER (11) 1 Vth 0 1 P 1 (10) Vth 1 P 2 (00) P 3 (01) MSB Program Vth 7

Basics of Program Interference (n+1, j-1) (n+1, j+1) WL<2> ∆Vxy MSB: 6 WL<1> ∆Vx MSB: 4 Victim Cell ∆Vx (n, j) WL<0> ∆Vxy (n-1, j-1) n LSB: 3 LSB: 1 MSB: 2 LSB: 0 (n-1, j) (n-1, j+1) Traditional model of victim cell threshold voltage changes when neighbor cells are programmed 8

Previous Work Summary n n No previous work experimentally characterized and modeled threshold voltage distributions under program interference Previous modeling work q Assumes linear correlation between the program interference q q q induced threshold voltage change of the victim cell and the threshold voltage changes of the aggressor cells Coupling capacitance and total capacitance of each flash cell are the key coefficients of the model, which are process and design dependent random variables Their exact capacitance values are difficult to determine Previously proposed model cannot be realistically applied in flash controller 9

Outline n n Background on Program Interference Characterization of Program Interference Modeling and Predicting Program Interference Mitigation of Program Interference q n Read Reference Voltage Prediction Conclusions 10

Characterization Hardware Platform Cai et al. , “FPGA-Based Solid-State Drive Prototyping Platform”, FCCM 2011 11

Characterization Studies n n Bitline to bitline program interference Wordline to wordline program interference q q Program in page order Program out of page order 12

Bitline to Bitline Program Interference P 1 State P 2 State P 3 State L= { P 0, P 1, P 2, P 3 } R= { P 0, P 1, P 2, P 3 } n n Vth distributions of victim cells under 16 ( 4 x 4) different neighbor values {L, R} almost overlap Bitline to bitline program interferences are small 13

WL to WL Interference with In-Page-Order Programming n n Program interference increases the threshold voltage of victim cells and causes threshold voltage distributions shift to the right and become wider Program interference depends on the locations of aggressor cells in a block q Direct neighbor wordline program interference is the dominant source of interference q Neighbor bitline and far-neighbor wordline interference are orders of magnitude lower 14

WL to WL Interference with Out-of-Page-Order Programming n The amount of program interference depends on the programming order of pages in a block q q In-page-order programming likely causes the least amount of interference Out-of-page-order programming causes much more interference 15

Comparison under Various Program Interference n Signal-to-noise ratio comparison Out-of-page-order Programming 16

Data Value Dependence of Program Interference n The amount of program interference depends on the values of both the aggressor cells and the victim cells 17

Outline n n Background on Program Interference Characterization of Program Interference Modeling and Predicting Program Interference Mitigation of Program Interference q n Read Reference Voltage Prediction Conclusions 18

Linear Regression Model n Feature extraction for Vth changes based on characterization q q n Threshold voltage changes on aggressor cell Original state of victim cell Enhanced linear regression model (vector expression) n Maximum likelihood estimation of the model coefficients 19

Model Coefficient Analysis n n Direct above cell dominance Direct diagonal neighbor second Far neighbor interference exists Victim cell’s Vth has negative affect 20

Model Accuracy Evaluation (x, y)=(measured before interference, measured after interference) Ideal if no interference With Systematic Deviation (x, y)=(measured before interference, predicted with model) Ideal if prediction is 100% accurate Without Systematic Deviation 21

Distribution of Program Interference Noise n Program interference noise follows multi-modal Gaussian-mixture distribution 22

Program Interference vs P/E Cycles n Program interference noise distribution does not change significantly with P/E cycles 23

Outline n n Background on Program Interference Characterization of Program Interference Modeling and Predicting Program Interference Mitigation of Program Interference q n Read Reference Voltage Prediction Conclusions 24

Optimum Read Reference for Flash Memory n Read reference voltage can affect the raw bit error rate f(x) g(x) f(x) State-A State-B g(x) State-A State-B Vth v 0 n vref v 1 Vth v 0 v’ref v 1 There exists an optimal read reference voltage q Predictable if the statistics (i. e. mean, variance) of threshold voltage distributions are characterized and modeled 25

Optimum Read Reference Voltage Prediction n Learning function (periodically, every ~1 k P/E cycles) q q n Program known data pattern and test Vth Program aggressor neighbor cells and test victim Vth after interference Optimum read reference voltage prediction q Default read reference voltage + Program interference noise mean

Raw bit error rate Evaluation Results 30% lifetime improvement 32 k-bit BCH Code (acceptable BER = 2 x 10 -3) No read reference voltage prediction With read reference voltage prediction n Read reference voltage prediction can reduce raw BER and increase the P/E cycle lifetime

Outline n n n Background of Program Interference Characterization Modeling and Predicting Program Interference Read Reference Voltage Prediction to Mitigate Program Interference Conclusions 28

Key Findings and Contributions n n Methodology: Extensive experimentation with real 2 Y-nm MLC NAND Flash chips Amount of program interference is dependent on q q q n n Location of cells (programmed and victim) Data values of cells (programmed and victim) Programming order of pages Our new model can predict the amount of program interference with 96. 8% prediction accuracy Our new read reference voltage prediction technique can improve flash lifetime by 30% 29

Program Interference in MLC NAND Flash Memory: Characterization, Modeling, and Mitigation Yu Cai 1 Onur Mutlu 1 Erich F. Haratsch 2 Ken Mai 1 Carnegie Mellon University 2 LSI Corporation 1