Processor Power Management Overview Agenda Introduction Overview of

Processor Power Management Overview

Agenda • Introduction • Overview of all power states Ø Global States Ø Device States Ø CPU States Ø PCIe Link PM States Ø Sleep States Ø AMT States Page 2

Agenda • Introduction • Overview of all power states Ø Global States Ø Device States Ø CPU States Ø PCIe Link PM State Ø Sleep States • Reset • Backup Page 3

Power Management under ACPI • Advanced Configuration and Power Management Interface • New concepts beyond APM − Fine granularity on CPU clock control − Multiple system sleeping states − Individual device management without H/W traps and timers − Thermal Management • Primary methodology for current power management. • Define Power States within the platform. – Lx States : Link States (for DMI and PEG) – Dx States : Device States – Cx States : CPU States. – Sx States : Sleep (System) States. – Mx States : ME (AMT)States. – Gx States : Global States. Page 4

Agenda • Introduction • Overview of all power states Ø Global States Ø Device States Ø CPU States Ø PCIe Link PM States Ø Sleep States • Reset • Backup Page 5

-Individual devices can be in Dx and processor can be in Cx G 3 : no power at all ( no battery or the system G 1/S 1: Stop Grant G 2/S 5: Soft Off is insufficient supply level to wake) G 1/S 3: Suspend to ram (STR) G 0/S 0/C 0: Full On G 1/S 4: Suspend to Disk (STD) G 0/S 0/C 1: Auto Halt G 0/S 0/C 2: Stop Grant G 0/S 0/C 3: Stop Clock G 0/S 0/C 4: Stop Clock with lower CPU voltage G 0(Working State) G 0/S 0/C 5 : Stop Clock with partial power off - System is running - Power is on Sleep / Hibernate Wake event OS initiate Power off G 1(Sleeping State) No System Traffic MCH, ICH and CPU off G 2(Soft Off) - No System Traffic - System is off - Small part of ICH remains on to accept wake up event. Global system state Page 6 PWR plug in & AFTERG 3_EN=0 G 3(Mech. Off) System is unplugged RTC battery continues to supply power to RTC PWR plug in & AFTERG 3_EN=1

Agenda • Introduction • Overview of all power states Ø Global States Ø Device States Ø CPU States Ø PCIe Link PM States Ø Sleep States • Reset • Backup Page 7

Device States : General D 0 Fully-On • This state is assumed to be the highest level of power consumption. The device is completely active. D 1 - D 2 Optional. Expected to save more power and preserve less device context than D 0. D 2 save more power than D 1 but the latency is high. D 3 Off - Power has been fully removed from the device. The device context is lost when this state is entered, so the OS software will reinitialize. Page 8

Agenda • Introduction • Overview of all power states Ø Global States Ø Device States Ø CPU States Ø PCIe Link PM States Ø Sleep States • Reset • Backup Page 9

CPU States : General C 0 Processor Power State – Normal state. While the processor is in this state, it executes instructions. C 1 -C 5 Processor Power State – Non executing power state. – The deeper the C state, the lower the power consumed by the processor in that state. • Processor power in C 1 is higher than the processor power in C 4. – The deeper the C state, the higher the entry and exit latency of that state • Entry/exit latency of C 4 is higher than that of C 1 Page 10

Intel CPU States State Entry Method Bus Masters Allowed Notes C 0 -- All o CPU is executing instructions C 1 Auto. Halt inst. All o Entered by CPU when it has nothing to do o Transparent to chipset C 2 Level 2 I/O read (Lv. L 2) All o ICH asserts STPCLK# o MCH may dynamically assert SLP# o Most CPU I/F signals are latched C 3 Level 3 I/O read (Lv. L 3) only isoc* o ICH asserts STPCLK#, DPSLP#, STP_CPU# o MCH or ICH asserts SLP# o Most CPU I/F signals are latched Break Event Interrupt events (SMI, SCI. . ) Interrupt (Key stroke, Mouse Movement, RTC) o Bus master snoop request o Unmasked interrupt: SMI#, NMI# o CPU break (FERR#) C 4 Level 4 I/O read (Lv. L 4) or C 4 on. C 3 only isoc* o ICH asserts STPCLK#, DPSLP#, STP_CPU#, DPRSTP#, DPRSLPVR o Bus master snoop request o MCH or ICH asserts SLP# o Unmasked interrupt: SMI#, NMI# o Most CPU I/F signals are latched o CPU break (FERR#) Page 11

Intel CPU States State Entry Method Bus Masters Allowed Notes Break C 5/C 6 Level 5/6 I/O read (Lv. L 5/Lv. L 6) All o CPU flushes cache prior to entry, so snoops aren’t necessary. CPU will be [almost] fully powered down. Interrupt events o ICH asserts STPCLK#, DPSLP#, STP_CPU#, DPRSTP#, DPRSLPVR, #PMSYNC o MCH or ICH asserts SLP# o Most CPU I/F signals are latched o Same pins as C 4, but different timings and abbreviated messaging Page 12

Intel® Deep Power Down Technology (C 6) Flexible C-States to Select Idle Power Level vs. Responsiveness Page 13

C 2 Entry/Exit Sequences Note: “M-I link” is DMI. “SG” message on “M-I link” should be “Req-C 2” Page 14

C 3 Entry Sequences Page 15

C 3 Exit Sequences Page 16

C 4 Entry Sequences Page 17

C 4 Exit Sequences Page 18

C 5/C 6 Entry Sequences Page 19

C 5/C 6 Exit Sequences Page 20

NHM CPU States • NHM supports C 0, C 1 E, C 3, C 6 and C 7. • C 7 is identical to C 6 at core level but different Uncore power optimization. • C 7 is an overall package state where all cores have lost their registers, last level cache is at its minimum voltage but uncore is still in retention voltage • On NHM, STPCLK#, SLP# and DPSLP# signals are removed due to platform change and CSI bus interface. • Not all package C-state will be supported on all versions of NHM like Uncore power reduction features on C 3 and lower power states maybe fused off in desktop or server parts. Page 21

Agenda • Introduction • Overview of all power states Ø Global States Ø Device States Ø CPU States Ø PCIe Link PM State Ø Sleep States Reset • Common Questions Page 22

Link PM States • L 0 – Active state • TLP(Transaction Layer Packet)’s and DLLP(Data Link Layer Packet)’s are permitted • L 0 s – Low resume latency, energy saving “standby” state: • no TLP/DLLP during L 0 s state • quick entry/exit, exit in the order of 100 ns for Intel chipset • L 0 s is single-directional. A transmitter can initiate L 0 s without the other port initiating L 0 s. • Main power and clocks remain. • Chipset gates some internal logic. • L 1 – lower power standby state – Higher latency PM state: • Downstream port initiates when the device power state is programmed to non D 0 state(D 3) • no TLP/DLLP during L 1 state. • Main power and clocks remain. • Exit in order of micro seconds. Page 23

Link PM States (Contd. . ) • L 2/3 ready – Staging point for L 2/L 3 – Required for PCIe PM before entering L 2 or L 3 state, this is not a real link state, it is just a phase requiring protocol handshake before entering L 2 or L 3. • A device must be in D 3 state before entering L 2/3 ready • System will place link L 2/3 ready state before entering S 3/S 4/S 5. • L 2 – Auxiliary powered Link deep energy state. L 2 is optionally supported. • Main power and clks are removed • the device has aux power to perform link reactivation through beacon, WAKE#, PME context and detection logic. • L 3 – Link off state. Zero power state. Page 24

Link PM States (Contd. . ) Summary of Link PM States: L-State Description Used By SW Directed PM Used By ASPM L 0 Fully Active Yes(D 0) Yes (D 0) L 0 s Standby No Yes(D 0) L 1 Lower Power Standby Yes(D 1 -D 3 hot) Yes(D 0) L 23 Ready Staging point for power removal Yes (links to PME_turn_off message ) No L 2 Low Power Sleep State Yes No L 3 Off (No Vaux) N/A No Ldn Transitional State before L 0 Yes No Page 25

Link PM States (Contd. . ) ASPM Control: Allows Hardware controlled PCIe dynamic link power reduction. Value Description 00 – Disabled • Port must not bring a Link into L 0 s state. • Port must not initiate a PM_active_State_Request_L 1 DLLP to other end of the link • Port receiving a L 1 request from other agent must respond with negative acknowledgement. 01 b – L 0 s Entry Enabled • Port must bring a Link into L 0 s state when all conditions are met. • Port must not initiate a PM_active_State_Request_L 1 DLLP to other end of the link • Port receiving a L 1 request from other agent must respond with negative acknowledgement. 10 b – L 1 Entry Enabled • Port’s transmitter must not bring a Link into L 0 s state. • Port may issue a PM_active_State_Request_L 1 DLLP to other end of the link • Port receiving a L 1 request from other agent must respond with positive acknowledgement. Page 26

Link PM States (Contd. . ) ASPM Control: Value Description 11 b – L 0 s and L 1 Entry Enabled • Port’s transmitter must bring a Link into L 0 s state. • Port may issue a PM_active_State_Request_L 1 DLLP to other end of the link • Port receiving a L 1 request from other agent must respond with positive acknowledgement. Page 27

Link PM States (Contd. . ) Relationship between Link and Device PM State. Device State Permissible Interconnect Link State D 0 L 0, L 0 s, L 1 (ASPM) D 1 L 1 D 2 L 2 D 3 hot L 1, L 2/L 3 ready D 3 cold L 2, L 3 Page 28

System and DMI Link Power States System States CPU State Description Link State SW Controlled S 0 C 0 Fully Operation. Opportunistic Link Active State L 0/L 0 s/L 1 N/A S 0 C 1 CPU Auto Halt L 0/L 0 s/L 1 Yes S 0 C 2 CPU Stop Clock L 0/L 0 s/L 1 Yes S 0 C 3 Deep Sleep: CPU’s clock halted via STP_CPU# assertion. MCH and ICH still being clocked L 0/L 0 s/L 1 Yes Page 29

System and DMI Link Power States System States CPU State Description Link State SW Controlled S 0 C 4 Deeper Sleep: CPU’s clock halted via STP_CPU# assertion and CPU’s voltage lowered. L 0/L 0 s/L 1 Yes S 1/S 1 D C 2 S 1 D same as C 2 L 0/L 0 s/L 1 Yes S 3/S 4/ S 5 N/A STR/STD/Off L 3 Yes Page 30

Agenda • Introduction • Overview of all power states Ø Global States Ø Device States Ø CPU States Ø PCIe Link PM State Ø Sleep States • Reset • Backup Page 31

Sleep States – User Point of View State Common Names Description S 1 Stand By, Entered by pressing sleep button, closing lid, system idle, etc. System appears mostly off (LED’s may indicate Stand By). Common wake events include power button, sleep button, mouse movement, modem ring, etc. System wakes quickly and all programs are still running. Powered on Suspend (refers to S 1 M state – last supported on ICH 5) S 2 S 3 Not supported by Intel chipsets Stand By, Suspend to RAM To user, appears the same as S 1, but in mobile system the battery can maintain S 3 much longer. Wake will take longer than S 1, but still very fast. S 3 is “suspend” when pressing Fn + F 4. S 4 Hibernate, Suspend to Disk Entered by user direction or system idle. System appears off. Most common wake event would be power button, but all others are still possible. System takes longer to wake than S 3, but all programs are still running. S 4 is “hibernate” when pressing Fn + F 12. S 5 Shut Down, Soft Off Page 32 Entered by user direction (Start -> Shut Down). Very similar to S 4, but a full boot occurs on wake (no programs remain running from previous S 0). Desktop must stay plugged in, laptop must have charged battery, otherwise platform is in G 3.

Sleep State Entry Sequence S 0 S 1 S 3 t 53 b STPCLK# DMI REQ - C 2 CPUSLP# Go C 2 - Ack - C 2 Go - S 3 t 56 +t 58 t 59 SLP_S 3# SLP_S 5# Page 33 L 3 t 55 PLTRST# SLP_S 4# L 2/ - S 3 t 53 c SUS_STAT# PWROK# Ack t 60 (for S 3 - Cold only) t 61 t 62 S 4 S 5

Sleep State Exit Sequence Page 34

Agenda • Introduction • Overview of all power states Ø Global States Ø Device States Ø CPU States Ø PCIe Link PM State Ø Sleep States Reset Ø AMT Status • Page 35

ME impact on Sleep States Page 36

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Thank You Page 40