Processor 0 Block State Processor 1 Tag Data

Processor 0 Block State Processor 1 Tag Data Block State Tag Data B 0 I 100 00 10 B 0 S 108 00 08 B 1 M 128 20 10 B 2 M 110 00 10 B 2 130 10 12 B 3 I 118 00 18 B 3 I I 120 10 28 Interconnect with Cache Coherency Manager Initial State Tag Block Data 100 108 110 118 120 128 130 132 134 00 10 00 08 00 10 00 18 10 28 20 10 10 12 40 12 10 22 Memory

Processor 0 Block State Processor 1 Tag Data Block State Tag Data B 0 S 128 20 10 B 0 S 108 00 08 B 1 S 128 20 10 B 2 M 110 00 10 B 2 130 10 12 B 3 I 118 00 18 B 3 I I 120 10 28 Interconnect with Cache Coherency Manager After reference 1: P 0: read 128 Tag Block Data 100 108 110 118 120 128 130 132 134 00 10 00 08 00 10 00 18 10 28 20 10 10 12 40 12 10 22 Memory

Processor 0 Block State Processor 1 Tag Data Block State Tag Data B 0 S 128 20 10 B 0 S 108 00 08 B 1 S 128 20 10 B 2 M 110 00 10 B 2 130 10 12 B 3 S 132 40 12 B 3 I S 132 40 12 Interconnect with Cache Coherency Manager After reference 2: P 1: read 132 Tag Block Data 100 108 110 118 120 128 130 132 134 00 10 00 08 00 10 00 18 10 28 20 10 10 12 40 12 10 22 Memory

Processor 0 Block State Processor 1 Tag Data Block State Tag Data B 0 M 128 20 15 B 0 S 108 00 08 B 1 I 128 20 10 B 2 M 110 00 10 B 2 130 10 12 B 3 S 132 40 12 B 3 I S 132 40 12 Interconnect with Cache Coherency Manager After reference 3: P 0: write 128 20 15 Tag Block Data 100 108 110 118 120 128 130 132 134 00 10 00 08 00 10 00 18 10 28 20 10 10 12 40 12 10 22 Memory

Processor 0 Block State Processor 1 Tag Data Block State Tag Data B 0 S 128 20 15 B 0 S 108 00 08 B 1 S 128 20 15 B 2 M 110 00 10 B 2 130 10 12 B 3 S 132 40 12 B 3 I S 132 40 12 Interconnect with Cache Coherency Manager After reference 4: P 1: read 128 Tag Block Data 100 108 110 118 120 128 130 132 134 00 10 00 08 00 10 00 18 10 28 20 10 10 12 40 12 10 22 Memory

Processor 0 Block State Processor 1 Tag Data Block State Tag Data B 0 S 128 20 15 B 0 S 108 00 08 B 1 S 128 20 15 B 2 M 110 00 10 B 2 130 10 12 B 3 S 132 40 12 B 3 I S 132 40 12 Interconnect with Cache Coherency Manager After reference 5: P 0: reads 110 Tag Block Data 100 108 110 118 120 128 130 132 134 00 10 00 08 00 10 00 18 10 28 20 10 10 12 40 12 10 22 Memory

Processor 0 Block State Processor 1 Tag Data Block State Tag Data B 0 S 128 20 15 B 0 S 108 00 08 B 1 S 128 20 15 B 2 S 110 00 10 B 2 B 3 S 132 40 12 B 3 S S 110 00 10 132 40 12 Interconnect with Cache Coherency Manager After reference 6: P 1: reads 110 Tag Block Data 100 108 110 118 120 128 130 132 134 00 10 00 08 00 10 00 18 10 28 20 10 10 12 40 12 10 22 Memory

Processor 0 Block State Processor 1 Tag Data Block State Tag Data B 0 S 128 20 15 B 0 S 108 00 08 B 1 S 128 20 15 B 2 S 110 00 10 B 2 B 3 S 132 40 12 B 3 S S 110 00 10 132 40 12 Interconnect with Cache Coherency Manager Memory after cache write-back: Tag Block Data 100 108 110 118 120 128 130 132 134 00 10 00 08 00 10 00 18 10 28 20 15 10 12 40 12 10 22 Memory