Preparatory Design Studies MRODX Use Xilinx Virtex II
- Slides: 13
Preparatory Design Studies MROD-X • Use Xilinx Virtex II Pro – Rocket. IO – Power. PC – Port the current MROD-In design from Altera to Xilinx Slide 1 ATLAS week: February 24, 2004 Peter Jansweijer
MROD-In design from Altera to Xilinx Altera APEX 20 K 200 EQC 240 -1 • Total logic elements – 5605 / 8320 (67 %) • Total ESB bits – 15360 / 106496 (14 %) • Total pins – 168 / 171 (98 %) Note 1: Note 2: Slide 2 Xilinx XC 2 VP 7 FG 456 -7 • Number of SLICEs – 2898 out of 4928 (58%) • Number of RAMB 16 s – 3 out of 44 (6%) • Number of External IOBs – 168 out of 248 (67%) Rule of thumb 70 % = FULL. If you try to put more in your FPGA then you’ll probably face routing and timing problems! 1 Xilinx “SLICE” (~ 2 “Logic Cells”) ~ 2 Altera “Logic Elements” ATLAS week: February 24, 2004 Peter Jansweijer
Virtex-II Pro Development Board Slide 3 ATLAS week: February 24, 2004 Peter Jansweijer
Virtex-II Pro Evaluation Kit Slide 4 ATLAS week: February 24, 2004 Peter Jansweijer
GOL Test Board Slide 5 ATLAS week: February 24, 2004 Peter Jansweijer
SFP Evaluation Kit Slide 6 ATLAS week: February 24, 2004 Peter Jansweijer
GOL to Rocket. IO test GOL Test Board Insert Start Reset Error 25 MHz Altera FPGA Event Data ROM Slide 7 GOL Development Board 50 MHz Xilinx Virtex-II Pro FPGA Event Data ROM 1 Gb/s Rocket IO =? ATLAS week: February 24, 2004 Status LEDs Idle Run Okay Fault Peter Jansweijer
GOL to Rocket. IO test Slide 8 ATLAS week: February 24, 2004 Peter Jansweijer
GOL to Rocket. IO test Results • Xilinx ISE Rocket. IO placement problem -> Solved • Back-annotated simulation (Smart-Models) of the setup -> Okay! Reset Start Insert Error + Start • Real life test -> Okay! Slide 9 ATLAS week: February 24, 2004 Peter Jansweijer
To Be Done: Test FPGA to FPGA Data Links Plus Flow Control Development Board Xilinx Virtex-II Pro FPGA Full Data Slide 10 FIFO Rocket IO Evaluation Kit 1. 6 Gb/s (160 MB/s) Xilinx Virtex-II Pro FPGA Rocket IO ATLAS week: February 24, 2004 FIFO Empty Data Peter Jansweijer
Power. PC core Evaluation • Learn to use Xilinx Embedded Development Kit (EDK) • Play with the demos that were delivered with the boards • Made LED On/Off via RS 232 system, using Power. PC core + Peripherals. Slide 11 ATLAS week: February 24, 2004 Peter Jansweijer
Power. PC Hello World System • • • Slide 12 PPC-Core PLB Arbitter PLB BRAM Controller BRAM PLB 2 OPB Bridge OPB Arbitter Processor Reset UART-Lite JTAG PPC controller Xilinx XC 2 VP 7 FF 869 -6 • PPC 405 s – 1 out of 1 100% • RAMB 16 s (2 KByte each) – 16 out of 44 36% • Number of SLICEs – 826 out of 4928 16% ATLAS week: February 24, 2004 Peter Jansweijer
Conclusions: • Design can easily be ported from Altera to Xilinx • Rocket. IO – GOL Receiver is working. – Inter FPGA link to be tested. • Power. PC – Consumes FPGA resources (probably need a XC 2 VP 20 instead of a XC 2 VP 7 device) – Needs investment in learning EDK – Needs investment in software development Slide 13 ATLAS week: February 24, 2004 Peter Jansweijer
