Practically Realizing Random Access Scan Anand S Mudlapur

Practically Realizing Random Access Scan Anand S. Mudlapur Department of Electrical and Computer Engineering Auburn University, AL 36849 USA 11/15/2005 MS Thesis Defence

Motivation for This Work • Serial scan (SS) test sequence lengths and test power consumption are increasing rapidly. – Reduction of test power and test time are complementary objectives in serial scan. • Scope of increasing delay fault coverage is limited in serial scan. • In spite of the advantages (test time, test volume, test power, and ease of testing for delay faults), random access scan (RAS) is not popular due to high overhead. 11/15/2005 MS Thesis Defence 2

Outline • Introduction to scan based testing – Advantages – Limitations • Introduction to RAS • Design of a new toggle RAS Flip-Flop • Highlight the uniqueness and feasibility of our design due to the reduction of two global signals 11/15/2005 MS Thesis Defence 3

Outline (contd. ) • A new scan-out structure • Analytical formulation of hardware overhead • Algorithm to compact test vectors • ATPG targeted for toggle RAS • Results on ISCAS Benchmark Circuits • Case study on an industrial circuit • Conclusion and future work 11/15/2005 MS Thesis Defence 4

Serial Scan: Most Popular DFT Method PI Combinational Circuit Scan-in FF FF FF PO Scan-out Test control (TC) 11/15/2005 MS Thesis Defence 5

Introduction to Serial Scan (contd. ) • Advantage: Enables application of combinational vectors to sequential circuits • Problems: – Clock cycles prohibitive as number of flip-flops increases – Scan-in often performed at a slow scan clock compared to functional clock of the circuit – Scan-in and scan-out cause undesirable circuit activity resulting in excessive power dissipation 11/15/2005 MS Thesis Defence 6

Test Power and Time of Serial Scan • Test power may exceed critical design limits. • All flip-flops are controlled and observed although a test may need those operation only on a subset of flip-flops. • Example: A circuit with 5, 000 Flip-Flops and 10, 000 combinational test vectors Total scan cycles = 5, 000 × 10, 000 + 5, 000 = 50, 015, 000 ! 11/15/2005 MS Thesis Defence 7

Solutions for Test Time Problem of Serial Scan • Partial scan [Agrawal et. al. 88] provides a trade off between ease of test generation and hardware cost of scan. Test power may still be a concern. • Vector compaction [Touba et. al. 00], may cause increased circuit activity resulting in higher power consumption. • Cross-Check [Gheewala et. al. 91] was a comprehensive test method for sequential circuits but the technology required dedicated routing layers for test wiring. 11/15/2005 MS Thesis Defence 8

Cross-Check • A grid architecture as shown in the adjoining figure • Flip-flops contents read out row-wise • Data from the flip-flops fed into a MISR 11/15/2005 MS Thesis Defence 9

Solutions for Test Power Problems of Serial Scan • Test scheduling for SOCs using power constraint [Chou et. al. 91]: Test parallelism reduces, increasing the test time. • Slow scan-clock [Chandra et. al. 94]: Test time increases. • ATPG based methods [Wang et. al. 94, Kajihara et. al. 02]: Result in lengthy test sequences. Contd. 11/15/2005 MS Thesis Defence 10

Further Solutions for Test Power (contd. ) • Modification of the order of scan cells or inserting inversion logic between scan cells after the test generation [Dabholkar et al. 98]; limited effect on test power. • Blocking hardware methods: Hold latch, blocking gates; have additional overhead. 11/15/2005 MS Thesis Defence 11

Delay Testing in Serial Scan • Delay testing in serial scan is highly constrained; may result in low fault coverage. • Enhanced scan flip-flops can make the application of arbitrary vectors possible. • This technique requires a hold-latch connected to each Flip-Flop in addition to a “HOLD” signal routed to every hold latch resulting in increased area overhead and signal delay in the scan path. 11/15/2005 MS Thesis Defence 12

Delay Testing in Serial Scan PI Combinational Circuit PO CK Scan-out CK TC HL HL HOLD V 1 settles SFF TC V 1 s-in Scan-in V 2 state scan-in V 1 V 2 Scan-out Test result latched CK TC 11/15/2005 MS Thesis Defence 13

Introduction to RAS • Random Access Scan (RAS) offers a single solution to the problems faced by serial scan (SS): – Each RAS cell is uniquely addressable for read and write. – RAS addresses both test application time and test power problems simultaneously • Previous and current publications on RAS: • • • Ando, COMPCON-80 Wagner, COMPCON-83 Ito, DAC-90 Baik et al. , VLSI Design-04, ITC-05, ATS-05, VLSI Design-06 Mudlapur et al. , VDAT-05, ITC-05 • Disadvantage: High routing overhead – test control, address and scan-in signals must be routed to all flipflops. 11/15/2005 MS Thesis Defence 14

Contributions of Present Work • Eliminate scan-in signal from circuit by using a new toggling RAS flip-flop. • Eliminate test control signal to flip-flops. • Provide a new scan-out architecture: – A hierarchical scan-out bus – An option of multi-cycle scan-out 11/15/2005 MS Thesis Defence 15

Random Access Scan (RAS) PI Address Inputs Combinational Circuit FF FF FF PO Scan-out bus Decoder These signals are eliminated in our design TC During every test, only a subset of all Flip-flops needs to be set and observed for testing the targeted faults Scan-in 11/15/2005 MS Thesis Defence 16

Conventional RAS Combinational Logic Data Scan-in M U X M Clock Mode S Combinational Logic Data RAS-FF Address Decoder Address Register 11/15/2005 MS Thesis Defence ACLK 17

New “Toggle” RAS Flip-Flop Combinational Logic Data 1 M U 0 X Combinational Logic Data M S Clock x y RAS-FF √nff Lines Row Decoder Address (log 2 nff) 11/15/2005 To Output BUS Control √nff Lines Column Decoder MS Thesis Defence 18

Toggle RAS Flip-Flop Operation Function Clock Normal Data Toggle Data Hold Data 11/15/2005 Address decoder outputs Row (x) Column (y) Active 0 0 Inactive 1 Active Clock Inactive Active Clock 1 Inactive 1 0 Inactive 0 1 Inactive 0 0 MS Thesis Defence 19

Toggle Flip-Flop Operation (contd. ) Unaddressed FFs x 4 Decoded address lines 11/15/2005 RAS FF 0 y 1 RAS FF 1 y 2 MS Thesis Defence Addressed FF RAS FF 01 y 3 20

Macro Level Idea of Signals to RAS-FF RAS FF 11 RAS FF 12 RAS FF 13 RAS FF 14 RAS FF 21 RAS FF 22 RAS FF 23 RAS FF 24 RAS FF 31 RAS FF 32 RAS FF 33 RAS FF 34 RAS FF 41 RAS FF 42 RAS FF 43 RAS FF 44 4 -to-1 Scan-out Macrocell x 1 x 2 x 3 x 4 11/15/2005 y 1 y 2 y 3 MS Thesis Defence y 4 To Next Level 21

Scan-out Macrocell • A 4 x 4 block scan-out data flow and control logic Data Bus From 4 RAS FFs To Next Level Output BUS { • D-FFs may be inserted at the two outputs of Control Signal to Next Level BUS Control From 4 RAS FFs macrocell for multi-cycle scan-out. 11/15/2005 MS Thesis Defence 22

Routing of Decoder Signals in RAS Address (log 2 √ nff) 11/15/2005 R O W Flip-Flops Placed on a Grid Structure D E C O D E R COLUMN DECODER MS Thesis Defence 23

Gate Area Overhead Gate area overhead of = Serial Scan Gate area overhead of Random Access Scan = where nff – Number of Flip-Flops ng – Number of Gates Assumption: D-FF contains 10 logic gates. 11/15/2005 MS Thesis Defence 24

Gate Area Overhead (Examples) 1. A circuit with 100, 000 gates and 5, 000 FFs Gate overhead of serial scan = 13. 3 % Gate overhead of RAS = 20. 0 % (Typical example from an industrial circuit. Details in later slide) 2. A circuit with 500, 000 gates and 5, 000 FFs Gate overhead of serial scan = 3. 6 % Gate overhead of RAS = 5. 5 % 11/15/2005 MS Thesis Defence 25

Overhead in Terms of Transistors Transistor overhead of = Serial Scan Transistor overhead of = Random Access Scan Where nt is number of transistors in comb. logic. D-flip-flop (28 transistors), serial scan FF (28+10) and RAS FF (28+26) were designed in 0. 5μ CMOS technology using Mentor Graphics Design Architect. 11/15/2005 MS Thesis Defence 26

Algorithm to Compact Test Vectors • Obtain the combinational vectors along with good circuit responses and store the results in a stack • Find the Flip-Flops where the faults are propagated at each vector • While number of vectors > 0 or remaining faults > 0 – Read all Flip-Flops where the faults are detected – Choose the next vector from stack that is at least hamming distance from current Flip-Flop states • End While 11/15/2005 MS Thesis Defence 27

Compaction of Test Vectors Stack 101 000 010 111 100 001 100 PI Address Inputs Combinational Circuit 0 RAS-FF 10 RAS-FF 01 RAS-FF PO Scan-out bus Decoder 11/15/2005 MS Thesis Defence 28

Test Time 11/15/2005 MS Thesis Defence 29

Test Power 11/15/2005 MS Thesis Defence 30

Case Study on an Industrial Circuit • • A case study on an industry circuit was performed at Texas Instruments India Pvt. Ltd. The preliminary results were as follows: 1. The gate area overhead of RAS for a chip with ~5500 Flip-Flops and ~100, 000 NAND equivalent gates was of the order of 18%. 2. 4 X reduction in test time was estimated. A speed-up of up to 10 X was considered possible using ATPG heuristics. 3. Estimated routing and device area overhead of RAS in physical layout was 10. 4%. 11/15/2005 MS Thesis Defence 31

Conclusion • New design of a “Toggle” Flip-Flop reduces the RAS routing overhead. • Proposed RAS architecture with new FF has several other advantages: – Algorithmic minimization reduces test cycles by 60%. – Power dissipation during test is reduced by 99%. • A novel RAS scan-out method presented. • For details on “Toggle” Flip-Flop, see Mudlapur et al. , VDAT-05. 11/15/2005 MS Thesis Defence 32

Backup Slides 11/15/2005 MS Thesis Defence 33

Thank you! 11/15/2005 MS Thesis Defence