Practical Strategies for PowerEfficient Computing Technologies Karim AlSheraidah

Practical Strategies for Power-Efficient Computing Technologies Karim Al-Sheraidah December 8 th 2011

Overview Survey of Power reduction techniques ~8 x improvement in power efficiency No performance lose Voltage Scaling Optimum VDD = 0. 5 V IBM Blue Gene system 2

Introduction The Regime of interest 3

Introduction cont… Pactive = Ceff V 2 ƒ + Ileak V Ceff is V dependent ƒ is linearly V dependent Ceff V 2 ∞ V 2. 5 ƒ = α(V – V 0) V 0 ≈ 0. 25 V Pactive = αCeff V 2 (V – V 0) + Ileak V ∞ V 3 4

The Case for Voltage Scaling Departing from scaling theory 5

The Case for Voltage Scaling Optimum VDD = 0. 5 v 6

The Case for Voltage Scaling cont… Optimum VDD = 0. 5 v 7

Enablement (1) Operating Margin improvement 8

Enablement (2) Low variability devices ET-SOI Fin-FET 9

Enablement (3) Digital Noise Resistive: d. VR/VDD = IR/VDD ∞ ( VDD – VT)1. 5/VDD Capacitive: d. VC/VDD = [Cagg. VDD/(Cagg + Cvic)]/VDD = C agg/(Cagg + Cvic) Inductive: d. VL/VDD = [ L ∂I/∂t ]/VDD ∞ (L I)/(VDDҭ) ∞ (V DD – V 0)( VDD – VT)1. 5/VDD 10

Enablement (4) On-Chip Power System 11

Case study (IBM Blue Gene) - Top 500 HPC from 2004 to 2007 - Operating at 850 MHz - Performance of up to 13. 9 Tflop - 4096 parallel processor cores - Three chip voltage bins 12

Conclusion - Power efficiency through voltage scaling. - Optimum VDD = 0. 5 v. - lowering of variability. - Increasing margin. - Massive parallelism. - High integration. 13