PPI Programmable Peripheral Interface Parallel port Interface 8255

8255 PPI

Addressing the 8255 A 1 A 0 = 01 = 10 = 11 Port A ; IN, OUT 8 bits at a time Port B ; IN, OUT 8 bits at a time Port C ; IN, OUT 8 bits at a time Control Register; Write ONLY! Addressing Example PORTA EQU 0224 h ; Port A 8255 PORTB EQU 0225 h ; Port B 8255 PORTC EQU 0226 h ; Port C 8255 STAT EQU 0227 h ; Control Port Another Addressing Example A 2 A 1(CPU) A 1 A 0(PPI) PORTA EQU 0224 h ; Port A 8255 PORTB EQU 0226 h ; Port B 8255 PORTC EQU 0228 h ; Port C 8255 STAT EQU 022 ah ; Control Port

Interfacing the 8255 8086 20 Address Only A 19 A 18 Address/Data A 17 AD 15 AD 7 A 16 AD 14 AD 6 AD 13 AD 5 +AD 12 AD 4 AD 11 AD 3 AD 10 AD 2 AD 9 AD 1 AD 8 AD 0 Address and Data lines are multiplexed in the 8086

Address and Data Buses 8086 20 ALE Address Latch 20 -bit address bus 16 Data Transceiver ALE is Address Latch Enable 16 -bit data bus

Addressing the 8255 IO/M 8 -bit data bus A 1 A 0 Data Port A RD 20 -bit address bus A 15 -A 2 8 WR RESET Logic Circuit CS A 1 A 0 Port B { Port C 8 4 CH CL 4

Logic Circuit • Inputs to the Logic Circuit – address lines A 15 - A 2 (the I/0 address space is 216 addresses, and A 1 and A 0 are used for the chip’s address lines) – the 8086’s IO/M line HIGH denotes an IO instruction (IN, OUT) LOW denotes a memory access instruction (i. e. , MOV) • Output of the logic circuit – a single low value from the 15 inputs (a NAND or OR gate) to activate the Chip Select • The connections for A 15 -A 2 fix the chip’s address in I/O space

8088 pins The 8088 is a 16 -bit microprocessor: Internal registers and buses are 16 bits wide 8 address/data lines 12 addresslines IO/M RD and WR

Minimum mode • In minimum mode, the 8086/8088 is the only microprocessor in the circuit. It can assume that it has control of memory, address, and data buses • In maximum mode, the 8086/8088 is configured for multiple microprocessors. The function of pins is changed to provide processor-to-processor communication

Reset • A single reset line is connected to all chips in the system (8088/8086, 8255, 8253, etc. ) • Reset puts the chip in a known state • Pushing the reset button on your computer generally activates RES pin of 8284 that outputs a high Reset pulse for a short period of time • On Reset, the 8088/8086 goes to fixed addresses (ROM chips) where boot sequence instructions are stored.

Basic Description of the 8255 • Its three I/O ports (labeled A, B, and C) are programmed in groups of 12 pins : • Group A connections consist of port A (PA 7 -PA 0) and the upper half of port C (PC 7 -PC 4) • Group B consists of port B (PB 7 -PB 0) and the lower half of port C(PC 3 -PC 0) • The 8255 is selected by its CS pin for programming, for reading or writing to a port. – Register selection is accomplished through the A 1 and A 0 input pins, which select an internal register for programming or operation

8255 A PPI – Parallel I/O Interface

8255 A PPI – Assets and Capabilities • 24 I/O lines in 3 8 -bit port groups – A, B, C • A, B can be 8 -bit input or output ports • C can serve as 2 4 -bit input or output ports • 3 modes of operation: – Mode 0: A, B, C simple input or output level sensitive ports – Mode 1: A, B input or output ports with strobe control in C – Mode 2: A is bidirectional with control/handshake in B and C • A, B can only change 1 byte at a time • C has individual bit set/reset capability Advantage is non-dedicated circuit can change port configuration with software and no “glue logic”

Mode Selection of the 8255 • Ports A, B, and C are used for I/O data. – The control register is programmed to select the operation mode of the three ports A, B, and C. – Mode 0 : simple I/O mode • Any of the ports A, B, CL and CU can be programmed as input or output. • No control of individual bits (all bits are out or all bits are in) – Mode 1 : Ports A and B can be used as input or output ports with handshaking. – Mode 2 : Port A can be used as bidirectional I/O port with handshaking

PPI Interface to CPU the PPI maps each of its 4 bytes to an address, but all connect to the same byte of the data bus; if data bus is 1 byte wide, they are consecutive addresses; if the bus is 2 bytes wide, they are mapped to alternate addresses; if the bus is 4 bytes wide, …etc.

Programming/Controlling the PPI • 8255 A PPI has a “write-only” control register, accessed when PPI’s A 0=A 1=1 (note: not A 0 and A 1 of the address bus!) • When PPI is reset (by an active-high strobe on its RESET pin): – Default is A, B, C are mode 0 input ports • Control register also used to set/reset port C bits individually

PPI Programming Example ; Assume address decoder designed for PPI base address 0400 h ; PPI is connected to D 7 -D 0 on CPU data bus mov dh, 04 h mov dl, 01 h mov al, 82 h out dx, al What does the code shown above do? ?

Control Word Example ; Assume address decoder designed for PPI base address 0400 h ; PPI connected to D 7 -D 0 on CPU data bus mov dh, 04 h ; Let dh point to base address mov dl, 03 h ; Select the control register mov al, 82 h ; Place 82 h Control Word into al out dx, al ; Write al contents to PPI ; explanation of operating mode set by this code ; D 7=1 Control Word (not a bit set/reset command) ; D 6 D 5=00 A and C 7 -C 4 are Mode 0 (Group A) ; D 4=0 A is Level Sensitive Output ; D 3=0 C 7 -C 4 are Level Sensitive Output ; D 2=0 B and C 3 -C 0 are Mode 0 (Group B) ; D 1=1 B is Level Sensitive Input ; D 0=0 C 3 -C 0 are Level Sensitive Output

8255 Connection to Stepper Motor

HW#2 • Sketch the schematic diagram for a 8086 minimum system that drives 8 seven segments through a PPI. • Port. A of PPI serves as the driver for the segments of a digit. (PA 0=a, PA 1=b, . . , PA 6=g, PA 7=‘. ’; • Port. B of PPI serves as the digit selection • Develop the SCAN Program. – Input: AL (0 to 7) the digit that should be shown – This routine is called every 10 ms • Due Date: Sunday 22 Farvardin 1389