Power Reduction Technique Parallelism in circuits using duplication

Power Reduction Technique Parallelism in circuits using duplication of logic ELEC 6270 By Sreekumar Menon

OUTLINE n n n n Problem Definition Steps for Implementation Background Information Experimental Results Theoretical Results Conclusion Lessons

Problem Definition n Design a 32 bit adder with parallelism Operational speed must be the same (throughput constant) Show it to be an effective Power reduction scheme

Block diagram Representation

Implementation Technique n MODELSim, Leonardo, Design Architect, Eldo Technology used ami 0. 5 Delay calculation( 50 % of the rise time) VHDL/Verilog n http: //www. amis. com/pdf/process_specifications/c 5_ss. pdf n n n

Power versus voltage (N=1) Voltage Dynamic Power (m. W) 5 22. 4128 Static Power (u. W) 33. 471 4 13. 1289 21. 020 3 7. 9665 11. 658 2 3. 7048 5. 114 1 0. 5181 1. 256

Dynamic Power v/s Voltage (N=1)

Power versus voltage (N=2) Voltage Dynamic Power (m. W) Static Power (u. W) 3. 5 18. 095 56. 18 3 12. 775 48. 11 2. 5 9. 0875 34. 62 2 6. 0511 22. 01 1. 5 2. 2306 14. 32

Dynamic Power v/s Voltage (N=2)

Delay versus Voltage (N=1) Voltage (Volts) Delay (Nano secs) 5 0. 34 4 0. 41 3 0. 608 2 1. 01 1 3. 77

Delay versus Voltage (N=1)

Experimental Results Delay (n. S) Voltage (N=1) Voltage (N=2) 0. 34 5 3 0. 41 4 2. 5 0. 608 3 1. 5 1. 01 2 NA

Power Reductions Voltage (V) Power (m. W) Reference voltage (V) Power (m. W) % Reduction 5 22. 41 3 12. 77 42. 99 4 13. 12 2. 0 6. 051 53. 39 3 7. 995 1. 5 2. 2306 72. 17 (N=2) (N=1)

Theoretical Calculations n Power = CVDD 2 n The Delay versus Voltage graph can be used for interpolating the voltage levels for various degrees of parallelism

Theoretical v/s Experimental Voltage (Reference) V Theoretical Value (V) Experimental Value (V) Power Reduction (Theoretical) % Power Reduction (Experimental )% 5 3. 2 3 52. 40 42. 99 4 2. 3 2. 5 64. 60 53. 39 3 1. 4 1. 5 78. 12 72. 17

Conclusions n n n Parallelism is an effective power reduction technique However, it causes extra designing effort The theoretical calculations do not exactly match because the overhead hasn’t been taken into account in it

Lessons n Patience!!!!!!!!!!!!!

References n n Dr Agrawal’s website Mentor manuals

n Thank You!!!!!