Power dissipation October 10 2017 Kjell Jeppson Lena

Power dissipation October 10, 2017 Kjell Jeppson, Lena Peterson Chapter 5 Power in W & H

Aim of the lecture • How is power dissipated in an integrated CMOS circuit – Dynamic power dissipation – Static power dissipation • Guidelines for reducing dynamic power dissipation – – Activity factor Capacitance – clock gating Supply voltage: multi-VDD Frequency: dynamic voltage scaling – – Reducing subthreshold leakage: multi-VT, stacking effect Reducing gate leakage: high-K materials, oxide thickness Junction leakage Power gating • Guidelines for reducing static power dissipation 2017 MCC 092: Integrated Circuit Design 2

Why care? 2017 MCC 092: Integrated Circuit Design 3

Power in vs power out on chip • Power grid • Clock grid • Cooling • Hot spots 2017 MCC 092: Integrated Circuit Design 4

Clock net 2017 MCC 092: Integrated Circuit Design 5

Power and energy • Power is drawn from a voltage source attached to the VDD pin(s) of a chip. • Instantaneous Power: • Energy: • Average Power: 2017 MCC 092: Integrated Circuit Design 6

Power and energy units • Power (work done per time unit) – Watts (W) = Joule/second (J/s) = Nm/s – 1 W = 1 VA = 1 VC/s • Energy (≈ the ability to do work) – 1 Joule (J) = 1 Nm = 1 Ws = 1 CV – Energy is often given in Whr = 3600 J – Note that work and energy has the same unit 2017 MCC 092: Integrated Circuit Design 7

Power in circuit elements EC is energy stored in Capacitor Note that it is ½ VQ 2017 MCC 092: Integrated Circuit Design 8

Charging a capacitor • When the gate output rises – Energy stored in capacitor: – Energy drawn from supply: – Half is dissipated in the p. MOS transistor as heat, other half stored in capacitor • When the gate output falls – Energy in capacitor is dumped to GND – Dissipated as heat in the n. MOS transistor 2017 MCC 092: Integrated Circuit Design 9

Voltages Currents Instantaneous power Energy W & H: Fig 5. 5 short-circuit current “blip” Example of switching waveforms: VDD = 1. 0 V, CL = 150 f. F, f = 1 GHz 2017 MCC 092: Integrated Circuit Design 11

Switching waveforms • Example: VDD = 1. 0 V, CL = 150 f. F, f = 1 GHz VDD VIN VDD VOUT i. DD i. LOAD v. IN CLOAD VSS v. OUT i. SC v. IN i. DD Ipeak i. SS Dynamic power dissipation: First p. MOS then n. MOS conducts Ipeak i. SS v. OUT CLOAD VSS Short-circuit power dissipation: Both transistors conduct at the same time i. LOAD t. SC

Switching power due to charging CL Energy per transition: Unit: Joules (J) Number of low-to-high transitions per second: Unit: 1/second CL Power: Unit: Joules/second = Watts 2017 MCC 092: Integrated Circuit Design 14

Activity factor • Suppose the system clock frequency = f • Let fsw = af, where a = activity factor – If the signal is a clock, a = 1 – If the signal switches once per cycle, a = ½ • Dynamic power: 2016 MCC 092: Integrated Circuit Design 15

Activity factor - definition = Probability that output switches from 0 to 1 = probability that node i is 1 = probability that node i is 0 If the probabilities are uncorrelated: For random data: so See W&H section 5. 2. 1 2016 MCC 092: Integrated Circuit Design 16

Power-dissipation sources • Ptotal = Pdynamic + Pstatic • Dynamic power: Pdynamic = Pswitching + Pshortcircuit – Switching load capacitances – Short-circuit current • Static power: Pstatic = (Isub + Igate + Ijunct + Icontention)VDD – – 2016 Subthreshold leakage Gate leakage Junction leakage Contention current MCC 092: Integrated Circuit Design 17

Short-circuit current • When transistors switch, both n. MOS and p. MOS networks may be momentarily ON at once • Leads to a blip of “short-circuit” current. • < 10% of dynamic power if rise/fall times are comparable for input and output • We will generally ignore this component • But if rise or fall times are long it may dominate! 2017 MCC 092: Integrated Circuit Design 18

Dynamic power: an example • 1 billion transistor chip – 50 M logic transistors • Average width: 12 l = 12 x 25 nm = 300 nm • Activity factor = 0. 1 – 950 M memory transistors • Average width: 4 l = 100 nm • Activity factor = 0. 02 – 1. 0 V 65 nm process – C = 1 f. F/mm (gate) + 0. 8 f. F/mm (diffusion) • Estimate dynamic power consumption @ 1 GHz. Neglect wire capacitance and short-circuit current. 2017 MCC 092: Integrated Circuit Design 19

Dynamic power: an example 1. 0 V 65 nm process C = 1 f. F/mm (gate) + 0. 8 f. F/mm (diffusion/parasitic) Estimate power dissipation at 1 GHz! 1 billion transistor chip 50 M logic transistors Average width: 300 nm Activity factor = 0. 1 950 M memory transistors Average width: 100 nm Activity factor = 0. 02 W & H: Example 5. 1 2017 MCC 092: Integrated Circuit Design 20

Dynamic power reduction • Try to minimize: 1. Activity factor 2. Capacitance 3. Supply voltage 4. Frequency 2017 MCC 092: Integrated Circuit Design 21

1. Reduce activity factor = Probability that output switches from 0 to 1 = probability that node i is 1 = probability that node i is 0 If probabilities are uncorrelated: For random data: so - Data is often not completely random - After AND or OR gates is lower than at inputs - Design dependent but typically See W&H section 5. 2. 1 2017 MCC 092: Integrated Circuit Design 23

Switching probabilities W&H: Table 5. 1 2017 MCC 092: Integrated Circuit Design 24

Textbook example 5. 2 a • A 4 -input AND is built out of two levels of gates • Estimate the activity factor at each node if the inputs have P = 0. 5 NAND 2: PY = 1 - PAPB 2017 NOR 2: PY = PA PB MCC 092: Integrated Circuit Design 25

Clock gating • The best way to reduce activity is to turn off the clock to registers in unused blocks = sleep mode – Saves clock activity (clock has a = 1) – Eliminates all switching activity in the block – Requires determining if block will be used 2017 MCC 092: Integrated Circuit Design 26

2. Reduce capacitance • Reduce gate capacitance – Fewer stages of logic – Small gate sizes • Reduce wire capacitance – Good floorplanning to keep communicating blocks close to each other – Drive long wires with inverters or buffers rather than complex gates 2017 MCC 092: Integrated Circuit Design 27

3. Reduce supply voltage – Multi -VDD Cache RAM 1. 2 V System-on-chip 0. 9 V CPU 1. 0 V 2017 MCC 092: Integrated Circuit Design 28

4. Reduce frequency • Do not run clock faster than necessary! • Multiple frequency domains – Often integer factors & synchronized clocks among domains • Lower clock frequency can be combined with smaller transistors and lower VDD which saves even more power. 2017 MCC 092: Integrated Circuit Design 29

Tradeoff: Textbook example 5. 3 • Generate an energy-delay trade-off curve for the circuit below as delay varies from the minimum possible (Dmin=23. 44 t) to 50 t. Assume all input probabilities are 0. 5. 2017 MCC 092: Integrated Circuit Design 30

Textbook example 4. 3 2017 MCC 092: Integrated Circuit Design 31

Textbook example 5. 3 2017 MCC 092: Integrated Circuit Design 32

Voltage domains • Run each block at the lowest possible voltage and frequency that meets performance requirements • Voltage domains – Provide separate supplies to different blocks Cache RAM 1. 2 V System-on-chip 0. 9 V CPU 1. 0 V 2017 MCC 092: Integrated Circuit Design 39

Voltage domains • Run each block at the lowest possible voltage and frequency that meets performance requirements • Voltage domains – Provide separate supplies to different blocks – Level converters required when crossing from low to high VDD domains 2016 MCC 092: Integrated Circuit Design 40

Dynamic voltage scaling (DVS) • Run each block at the lowest possible voltage and frequency that meets performance requirements • Voltage domains – Provide separate supplies to different blocks – Level converters required when crossing from low to high VDD domains • Dynamic Voltage Scaling – Adjust VDD and f according to workload 2017 MCC 092: Integrated Circuit Design 41

Conclusion dynamic power reduction 1. Activity factor • • Clock gating Reduce logic depth –> reduced glitching 2. Capacitance • • Minimum transistor sizes Short wires 3. Supply voltage • • Multiple VDD domains Dynamic voltage/frequency scaling 4. Frequency • • 2017 Multiple clock domains Dynamic voltage/frequency scaling MCC 092: Integrated Circuit Design 42

From DAT 093 2017 MCC 092: Integrated Circuit Design 43

From DAT 093 2017 MCC 092: Integrated Circuit Design 44

Static power • Static power is consumed even when chip is quiescent. – Leakage draws power from nominally OFF devices VDD 4. Contention current (in NMOS) VOUT 2. Gate leakage 3 Drain leakage VSS 1. Sub-threshold leakage 2017 MCC 092: Integrated Circuit Design 45

Reducing sub-VT leakage: Multi-VT • In 65 nm processes and below, libraries with multiple (typically 3) VT has become a common way of reducing leakage currents. 2017 MCC 092: Integrated Circuit Design 46

Static power: textbook example 5. 4 Subthreshold leakage: SVT: 100 n. A/mm; HVT: 10 n. A/mm Gate leakage: 5 n. A/mm; Junction leakage: negligible Estimate static power consumption! 1 billion transistor chip 50 M logic transistors Average width: 300 nm Activity factor = 0. 1 5% standard VT (SVT), 95% high-VT (HVT) 950 M memory transistors Average width: 100 nm Activity factor = 0. 02 All MOSFETs are high-VT (HVT) 2017 MCC 092: Integrated Circuit Design 47

Static power: textbook example 5. 4 Solution: Assumption half of transistors are ON and give gate leakage) half are OFF give subthreshold leakage) • 860 m. W is 14% of the 6. 1 W dynamic power calculated earlier! • Will deplete battery of handheld device rapidly 2017 MCC 092: Integrated Circuit Design 48

Subthreshold leakage • For VDS > 50 m. V • Ioff = leakage at Vgs = 0, VDS = VDD 1 E+02 1 E+01 1 E+00 Typical values in 65 nm Ioff = 100 n. A/mm @ VT = 0. 3 V Ioff = 10 n. A/mm @ VT = 0. 4 V Ioff = 1 n. A/mm @ VT = 0. 5 V s = 0. 1 V-1 Subthreshold slope: S = 100 m. V/decade VDS=1, 2 V IDS 1 E-01 VDS=0, 05 V 1 E-02 1 E-03 1 E-04 1 E-05 1 E-06 -0. 2 2016 0. 3 VGS 0. 8 MCC 092: Integrated Circuit Design 49

Subthreshold leakage – stacking effect VDD VDD Two ON MOSFETs in series VX →Current reduced to ION/2 i. e. a factor of 2 reduction! VDD VSS VX VSS VSS Two OFF MOSFETs in series Subthreshold current reduced to IOFF/10. A factor of 10 reduction! 1 E+02 How can that be? 1 E+01 1 E+00 VDS=1, 2 V IDS 1 E-01 VDS=0, 05 V 1 E-02 1 E-03 1 E-04 1 E-05 1 E-06 -0. 2 2016 0. 3 VGS 0. 8 MCC 092: Integrated Circuit Design 50

Subthreshold leakage • Series OFF transistors have less leakage – Vx > 0, so N 2 has negative Vgs – Leakage through 2 -stack reduces ~10 x – Leakage through 3 -stack reduces further 2016 MCC 092: Integrated Circuit Design 51

2. Gate leakage • Extremely strong function of tox and VGS – Negligible for older processes – Approaches subthreshold leakage at 65 nm and below in some processes • An order of magnitude less for p. MOS than n. MOS • Control leakage in the process using tox > 10. 5 Å – High-k gate dielectrics help – Some processes provide multiple tox • e. g. thicker oxide for 3. 3 V I/O transistors • Control leakage in circuits by limiting VDD 2017 MCC 092: Integrated Circuit Design 52

NAND 3 leakage variation due to input pattern • 100 nm process Gate leakage: Ign = 6. 3 n. A, Igp = 0 Subthreshold leakage: Ioffn = 5. 63 n. A, Ioffp = 9. 3 n. A More than two orders of magnitude difference in leakage current! Table 5. 2 In W&H All current values are in n. A 2017 MCC 092: Integrated Circuit Design 53

3. Junction leakage • From reverse-biased p-n junctions – Between diffusion and substrate or well • Ordinary diode leakage is negligible • Band-to-band tunneling (BTBT) can be significant – Especially in high-VT transistors where other leakage is small – Worst at Vdb = VDD • Gate-induced drain leakage (GIDL) exacerbates – Worst for Vgd = -VDD (or more negative) 2017 MCC 092: Integrated Circuit Design 54

How to reduce: Supply gating • Turn OFF power to blocks when they are idle to save leakage – Use virtual VDD (VDDV) – Gate outputs to prevent invalid logic levels to next block • Voltage drop across sleep transistor degrades performance during normal operation – Size the transistor wide enough to minimize impact • Switching wide sleep transistor costs dynamic power – Only justified when circuit sleeps long enough 2017 MCC 092: Integrated Circuit Design 55

Leakage control • Leakage and delay trade off – Aim for low leakage in sleep and low delay in active mode • To reduce leakage: – Increase VT: multiple VT • Use low VT only in delay critical circuits – Increase Vs: stack effect • Input vector control in sleep – Decrease Vb • Reverse body bias in sleep • Or forward body bias in active mode 2017 MCC 092: Integrated Circuit Design 56

Summary Dynamic (active) is mainly due to switching: Static is mainly due to subthreshold leakage : Exponential dependence Modern power reduction techniques require knowledge about high-level aspects of the application 2017 MCC 092: Integrated Circuit Design 57