Power Bus Design Optimization Using PSPICE and Taguchi
Power Bus Design Optimization Using PSPICE and Taguchi by Mr. Andrew G. Bell Mrs. Catherine M. Vincent ITT Industries SSD Fort Wayne, Indiana Opt - 1
Introduction © ITT Space Systems Division (SSD) ØRochester, New York ØFort Wayne, Indiana ØClifton, New Jersey ØBoulder, Colorado ØVienna, Virginia © Rochester, NY (HQ) Fort Wayne, IN 2, 474 employees Boulder, CO Opt - 2 Clifton, NJ Vienna, VA
Introduction © © Products § Intelligence, Surveillance and Reconnaissance (ISR) § Image Information § Space Science and Commercial Remote Sensing § Meteorological and Navigational Space Payloads Topic § Optimization process for power busses Opt - 3
Objectives and Benefits © Objectives § Power Bus optimization using ØAnalysis of Means “ANOM” (Taguchi) ØPSPICE running in a batch mode © Benefits § Optimization ensures highest quality design for the customer § Cost reduction by saving time Opt - 4
Approach © Use Analysis of Means (ANOM) § L 18 orthogonal array for eight control factors § L 4 orthogonal array for three noise factors § Use the smaller-the-better signal to noise ratio © Run simulations in a batch mode using PSPICE © Perform confirmation runs to evaluate optimal solution Opt - 5
Example Power Bus Minimize both inrush current and output voltage drop length & wire gauge Baseline Performance: Inrush Current 19. 16 A Output Voltage Drop 1. 18 V Noise Factors Control Factors Opt - 6
Control and Noise Factors Control Factors Symbol Description Level 1 Level 2 Level 3 A Chassis Impedance (RC) 0. 001 (ohms) 0. 01 (ohms) N/A B Cable Length (LENGTH) 12 (in. ) 24 (in. ) 36 (in. ) C Cable Wire Diameter (WD) 0. 04 (in. ) 0. 051 (in. ) 0. 064 (in. ) D R 1 4. 7 K (ohms) 5. 6 K (ohms) 6. 8 K (ohms) E R 2 1. 8 K (ohms) 2. 7 K (ohms) 3. 9 K (ohms) F C 1 0. 10 m (farads) 0. 22 m (farads) 0. 056 m (farads) G Symbol H X Noise Factors R 4 10 (ohms) 15 (ohms) Description Level 1 T 1 (Turn On Rise Time) Vin (Bus Input Voltage) 1 n (sec) 5 n (sec) 22 (Volts) 22 (ohms) Level 2 10 n (sec) 34 (Volts) Y Load Resistance (RL) 30 (Ohms) 10 (Ohms) Z Load Capacitance (CL) 15 m (farads) 47 m (farads) Opt - 7
Experimental Layout • Control Factor L 18 OA • Noise Factor L 4 OA • One experiment for inrush current • One experiment for output voltage drop • STB (Smaller the Better Optimization) Opt - 8
Smaller Best S/N Calculation: Inrush Current yi = each value determined for each run n = 4 (four groups run for each of the 18 runs) Opt - 9
Smaller Best S/N Calculation: Output Voltage Drop yi = each value determined for each run n = 4 (four groups run for each of the 18 runs) Opt - 10
Factor Level Average Graphs (ANOM) Factor Effect Plot Inrush Current Factor Effect Plot Output Voltage Drop Opt - 11
Confirmation Trials • Build 3 simulation schematics for each of the noise factor settings • Do comparison of inrush current and output voltage drop for best combination STB • Record optimization results for combination STB, Current STB and Voltage STB Opt - 12
Confirmation Trial Results inrush current output voltage drop • Largest S/N ratio for inrush current (23. 8 d. B) is Conf-I • Largest S/N ratio for output voltage drop (-4. 49 d. B) is Conf-V • Best S/N compromise for inrush current (-23. 83 d. B) and output voltage drop (-4. 61 d. B) is Conf. Comb Opt - 13 -23. 80 d. B = 14. 3 A -23. 83 d. B = 14. 4 A -25. 90 d. B = 18. 8 A -4. 49 d. B = 1. 48 V -4. 61 d. B = 1. 50 V -4. 89 d. B = 1. 55 V
Conclusions and Benefits t Optimal power bus design in less time and reduced cost t PSPICE in batch mode reduces simulation time and reduces cost t ANOM determines optimal control factor settings for best design Opt - 14
Acknowledgements © Thanks to § Eric Smith § George Adamczyk Opt - 15
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