Polynomial Construction for Arithmetic Circuits Alan Mishchenko Robert

Polynomial Construction for Arithmetic Circuits Alan Mishchenko Robert Brayton Department of EECS UC Berkeley

Overview l l l Introduction Half-adder and full-adder Adder tree detection Polynomial construction Using polynomials in verification Conclusion 2

Introduction l Arithmetic circuit verification is the problem of proving that l l l l a given circuit implements a known arithmetic function two circuits containing arithmetic functions are equivalent It is one of the remaining strongholds in the well-studied field of formal verification and equivalence checking Many approaches have been tried, none of them seems to work well in practice This work is motivated by the need to have a reliable practical solution The most general approach is not practical, therefore… Assumption: cut-points between adders are preserved in the circuit structure

Terminology l AIG is an And-Inverter Graph l l l AIG variable is a node in the AIG l l l a node can be constant 0, a primary input, a two-input AND gate AIG literal is a AIG variable with a complemented attribute Bit-blasting is a process of translation into an AIG l l simple circuit data-structure only combinational AIGs are considered here word-level operators such as adders, multipliers, selectors, etc are bit-blasted into equivalent networks composed of AIG nodes and included in the AIG representing the design CEC stands for combinational equivalence checking CEC miter is a combinational circuit whose output is equal to 0 iff two circuits are indeed equivalent LHS and RHS are parts of the CEC miter representing two copies of the design being compared

Half Adder A, B Carry Sum 00 0 0 01 0 1 10 0 1 11 1 0 XOR = a * !b + !a * b = !(!a * !b + a * b) = !(!a * !b) * !(a * b) Sum Carry HA Sum Carry 3 AND 2 nodes

Full Adder Sum A, B, C Carry Sum 000 0 0 001 0 1 010 0 1 011 1 0 100 0 1 101 1 0 110 1 0 111 1 1 Sum Carry Sum HA Carry FA Carry Sum HA A B 7 AND 2 nodes C

Adder Tree l l l cin Adder is a full-adder or a half-adder Adder tree (AT) is one or more adders feeding into each other, without any intermediate logic gates Example 1: Ripple-carry adder (RCA) Example 2: An array of RCAs adding partial products of a multiplier Example 3: Wallace tree adding partial products of a multiplier s 0 s 1 s 2 s 3 FA FA a 0 b 0 a 1 b 1 a 2 b 2 a 3 b 3 cout Ripple-carry adder Wallace tree of adders

Multiplier l Multiplier is composed of the following blocks Product Adder tree Final stage adder (twoargument adder) Partial product accumulator (multi-argument adder) Partial product generator Multiplicants

Adder Tree Detection l In this presentation, we assume that an adder tree is detected by reverse-engineering l l inputs/outputs and their polarity/order are known internal cut-points between FAs/HAs are known Combinational logic Adder tree Combinational logic

Polynomial Construction Rules !a a & b => => 1 – a ab l a | b a ^ b => => a + b - ab a + b - 2 ab l MUX(a, b, c) => = = ab | (1 - a)c ab + (1 -a)c - ab(1 -a)c ab + c - ac l l l

Polynomial Construction l l Performed from outputs to inputs It is important for smooth construction to have correct order, polarity and signedness of the outputs l l It is important for smooth construction to move through cuts, which cross logic only one FA/HA at a time l l Otherwise polynomial will explode After constructing polynomial in each cut, it should be “clean” l Each monomial has only one literal and coefficient equal to the degree of 2

Using Polynomials to Verify Against the Specification l Input: Polynomial constructed for a circuit and the specification of this circuit as an arithmetic expression Output: Result of checking their equivalence l Solution: l l l Construct polynomial for the specification Compare polynomial for the circuit with that for the specification

Conclusion l l l Presented an approach to arithmetic circuit verification Procedures are being implemented in ABC and tested on industrial designs Future work includes extending the methodology to work for the case when the cut-points between adders are not present in the AIG