Plenary 2008 IEEECSIC Symposium October 12 2008 THz

Plenary, 2008 IEEE-CSIC Symposium, October 12, 2008 THz Bipolar Transistor Circuits: Technical Feasibility, Technology Development, Integrated Circuit Results Mark Rodwell University of California, Santa Barbara Coauthors E. Lobisser, M. Wistey, V. Jain, A. Baraskar, J. Koo University of California, Santa Barbara E. Lind Lund University Z. Griffith, J. Hacker, M. Urteaga, D. Mensa, Richard Pierson, B. Brar Teledyne Scientific Company rodwell@ece. ucsb. edu 805 -893 -3244, 805 -893 -5705 fax

( ! ) Law) is Near (? ) The End is (of. Near Moore's It's a great time to be working on electronics ! Things to work on: In. P HEMTs & HBTs: extend (f , fmax) to 2 -3 THz, build THz ICsdevelop V- and W-band power Ga. N HEMTs: amplifiers Si MOSFETs: work to keep them scaling past 22 nm CMOS IC design: build ICs which bury the III-V's In. Ga. As MOSFETs: help keep VLSI scaling (maybe)

Scaling for THz Transistors

Simple Device Physics: Resistance bulk resistance contact resistance -perpendicular contact resistance - parallel Good approximation for contact

Simple Device Physics: Depletion Layers capacitance transit time spacecharge limited current

Simple Device Physics: Thermal Resistance Exact Carslaw & Jaeger 1959 Long, Narrow HBT Emitter, FET Gate Stripe Square ( L by L ) IC on heat sink

Simple Device Physics: Fringing Capacitance wiring capacitance VLSI power-delay FET parasitic capacitances FET scaling

Frequency Limits and Scaling Laws of (most) Electron Devices PIN photodiode To double bandwidth, reduce thicknesses 2: 1 Improve contacts 4: 1 reduce width 4: 1, keep constant length increase current density 4: 1

Bipolar Transistor Design

Bipolar Transistor Design

Bipolar Transistor Design: Scaling

Bipolar Transistor Scaling Laws Changes required to double transistor bandwidth: parameter collector depletion layer thickness base thickness emitter junction width collector junction width emitter contact resistance current density base contact resistivity change decrease 2: 1 decrease 1. 414: 1 decrease 4: 1 increase 4: 1 decrease 4: 1 Linewidths scale as the inverse square of bandwidth because thermal

Thermal Resistance Scaling : Transistor, Substrate, Package

Thermal Resistance Scaling : Transistor, Substrate, Package Probable best solution: Thermal Vias ~500 nm below In. P subcollector. . . over full active IC area.

In. P Bipolar Transistor Scaling Roadmap indust universityappear ry y 2007 -8 s →industr feasibl y e maybe emitter 512 16 256 8 128 4 64 2 32 nm width 1 m 2 access r base 300 20 175 10 120 5 60 2. 5 30 nm contact width, 1. 25 m 2 contact r collector 4. 5 150 9 106 18 75 36 53 37. 5 nm thick, 72 m. A/ m 2 current 4 3. 3 2. 75 2 -2. 5 V, breakdown 520 850 245 150 730 1300 430 240 1000 2000 660 330 1400 GHz 2800 GHz 1000 1400 GHz 480 660 GHz density 4. 9 ft 370 fmax 490 power amplifiers digital 2: 1 divider

Can we make a 1 THz Si. Ge Bipolar Transistor ? In. P Simple physics clearly drives scaling emitter 64 transit times, Ccb/Ic 2 → thinner layers, higher current r density high power density → narrow base 64 junctions width, small junctions→ low resistance 2. 5 contacts r Key challenge: Breakdown 15 nm collector → very low breakdown (also need better Ohmic contacts) Si. Ge 18 1. 2 nm width m 2 access 56 nm contact 1. 4 m 2 contact collector 36 2. 75 53 125 ? ? ? 15 nm thick m. A/ m 2 V, breakdown ft fmax 1000 2000 GHz 1000 2000 PAs 1000 GHz Assumes collector junction 3: 1 wider digital 480 GHz than emitter.

HBT Design For IC Performance from charge-control analysis:

In. P HBT: Status

In. P DHBTs: September 2008 125 nm 250 nm 600 n m 350 nm

512 nm In. P DHBT Laboratory Technology 500 nm mesa HBT 150 GHz M/S latches UCSB / Teledyne / GCS Production 175 GHz amplifiers UCSB 500 nm sidewall HBT DDS IC: 4500 HBTs 20 -40 GHz opamps Teledyne / BAE ( Teledyne ) Z. Griffith M. Urteaga P. Rowell D. Pierson B. Brar V. Paidi f = 405 GHz fmax = 392 GHz Vbr, ceo = 4 V Teledyne / UCSB 20 GHz clock 53 -56 d. Bm OIP 3 @ 2 GHz with 1 W dissipation

256 nm Generation In. P DHBT 150 nm thick collector 70 nm thick collector 324 GHz Amplifier 60 nm thick collector 200 GHz master-slave latch design Z. Griffith, E. Lind J. Hacker, M. Jones

324 GHz Medium Power Amplifiers in 256 nm HBT ICs designed by Jon Hacker / Teledyne 256 nm process flow. Hacker et al, 2008 IEEE MTT-S ~2 m. W saturated output power

128 / 64 / 32 nm HBT Technologies

Conventional ex-situ contacts are a mess THz transistor bandwidths: very low-resistivity contacts are required with surface oxidewith metal textbook penetration contact Interface barrier → resistance Further intermixing during high-current operation → degradation

Improvements in Ohmic Contacts 128 nm generation requires ~ 4 - μm 2 emitter & base resistivities 64 nm generation requires ~ 2 - μm 2 Contacts to N-In. Ga. As*: Mo MBE in-situ 0. 3 (+/- 0. 7) - μm 2 Ti. W ex-situ / NH 4 pre-clean ~1 to 2 μm 2 variable between process runs Contacts to P-In. Ga. As: Mo MBE in-situ below 2. 5 - μm 2 Pd/Ti. . . ex-situ ~4 - μm 2 *measured emitter resistance remains higher than that of

Mo Emitter Contacts: Robust Integration into Process Flow Proposed Process Integration:

Process Must Change Greatly for 128 / 64 / 32 nm Nodes control undercut → thinner emitter thinner base metal → excess base metal resistance Undercutting of emitter ends {101}A planes: fast {111}A planes: slow

128 nm Emitter Process: Dry Etched Metal & Semiconductor Lith o pattern metal sidewall dry etch wet etch Recent Results @ 128 nm emitter width to be submitted results @ c. a. 200 nm emitter metal width

Planarization E/B Processes for 64 & 32 nm Planarization boundary

What about In. Ga. As HEMTs ? . . . & In. Ga. As MOSFETS ?

In. Ga. As HEMTs and In. Ga. As MOSFETs high-K gate barrier Source Gate N+ source/ drain by MBE regrowth Drain K Shinohara sub-22 -nm In. Ga. As MOSFETs being developed for potential use in VLSI Efforts may: improve understanding HEMT & MOSFET scaling limits produce process modules which aid THz Key III-V MOSFET scaling limits: HEMTslow density of states→limits g → C m fringing/gm does not scale low. HEMT m* → scaling high well energy → minimum well thickness Additional limits: high access resistance: barriers, recess regions, contacts

HBT Applications

Applications of THz In. P HBTs Mixed-Signal ICs (ADCs, DACs, DDS) benefit in high-clock-rate ICs with 1 k-3 k devices lack of CMOS integration a major limitation → Mark Rosker's talk Precision GHz analog ICs using THz transistors → Sanjay Raman's talk , Zach Griffith's talks mm-Wave Power: 60 GHz & up Ga. N threatens, but fmax→ gain → PAE 600 -1000 GHz transceiver ICs for low-volume military / scientific applications

Few-THz Bipolar Transistors THz In. P Bipolar Transistors: can it be done ? Scaling limits: contact resistivities, device and IC thermal resistances. 62 nm (1 THz f , 1. 5 THz fmax ) scaling generation is feasible. 700 GHz amplifiers, 450 GHz digital logic Is the 32 nm (1 THz amplifiers) generation feasible ? THz In. P Bipolar Transistors: what would we do with it ? Mixed-Signal IC Power density & CMOS integration are serious challenges Precision GHz analog systems mm-wave power Sub-mm-wave electronics