Pixel Electronics slides for UCSC Cover 0 13

Pixel Electronics slides for UCSC Cover 0. 13 FE chip ROD Other Activities (except DC-DC) May 2007 Pixel Electronics --- US ATLAS Upgrade R&D --- Garcia-Sciveres 1

Progress in FY 07 • • Epilogue from 2004 test chip Preamp chip submission & testing Workshop at CERN Work-plan for full size chip submission – Includes non-US manpower • CPPM: • Bonn: • Genova: – US to focus on unique capabilities • Analog design • Architecture • Full chip integration May 2007 Pixel Electronics --- US ATLAS Upgrade R&D --- Garcia-Sciveres 2

2004 test chip epilogue • CPPM has prepared an SEU measurement setup using the LBNL 2004 0. 13 um test chip. • They are irradiating with 20 Ge. V protons at CERN right now to extend the studies done at the LBNL 88” cyclotron in FY 06. • LBNL simply provided test boards, a few chips, and advice, but we are getting a great deal in return • More on collaboration with European institutes later… May 2007 Pixel Electronics --- US ATLAS Upgrade R&D --- Garcia-Sciveres 3

Analog test chip submitted Feb. 07 – resistor continuous reset. – current source continuous reset. • nominal current 22 m. A/pixel 3. 6 mm • 130 nm bulk CMOS • 840 pixels complete with threshold and bias registers. • 2 basic charge-integrating amplifier designs: – Goal for final chip is ~10 m. A/pixel • Simulated ENC ~200 e- for 400 f. F input load and ~20 ns peaking time – Exact value depends on many tunable parameters May 2007 2. 8 mm Pixel Electronics --- US ATLAS Upgrade R&D --- Garcia-Sciveres 4

Analog test chip plans • • Expected chip delivery late May Test board in fabrication now Initial “checkout” by Abder at LBNL Distribution of chips to other test efforts in June/July – Interest from European collaborators to participate in testing • Some irradiation possible in FY 07, but mainly in 08 – Hope that European colleagues will set up irradiation tests in FY 08 - no project fund request for this. – Note that all transistors are linear (with guard rings around Nmos) • Critical initial measurements expected – Threshold dispersion – Uniformity across array. Operating margin. – Current consumption, noise and timewalk May 2007 Pixel Electronics --- US ATLAS Upgrade R&D --- Garcia-Sciveres 5

Pixel Upgrade Electronics Workshop • Held on March 22 at CERN following ATLAS-CMS Electronics (ACES) workshop. http: //indico. cern. ch/conference. Display. py? conf. Id=13957 • 7 electical engineers not presently involved in pixels attended this meeting – CPPM, Bonn, Nikef, Genova – Clearly there is interest • Work Plan drafted in April to foster efficient collaboration – First global chip designers’ pone meeting to go over this plan isnext week May 2007 Pixel Electronics --- US ATLAS Upgrade R&D --- Garcia-Sciveres 6

Plans for FY 08 • Work-plan milestones – – Architecture definition: September 2007 Initial Design review: January 2008 Final Design review: September 2008 First full size chip submission: December 2008 • LBNL engineering manpower – – 100% Abder Mekkaoui: Lead IC designer, analog front end, integration 40% Dario Gnani: IC designer, High level description, readout logic 30% George Chao: Pad frame 10% Peter Denes: Organization, pads. (no cost to project) • LBNL purchases/fabrications – Assume a second iteration of front end design (if nothing else to fine tune lower current modifications): $65 K including test board. May 2007 Pixel Electronics --- US ATLAS Upgrade R&D --- Garcia-Sciveres 7

FY 09 • Continue same level of design effort until submission – For Dec. submission this is 25% of FY 08 manpower cost • Reduced effort still needed after submission in FY 09 for simulation and testing – Take 50% of FY 08 cost for remaining 75% of FY 09 • Finally need to cover test board design (based on existing TPLL) and fabrication – EE, drafter, and board fab cost. – Student-like personnel to operate test setup • Cost of engineering run to be paid out of BL replacement ATLAS project, which is M&O-B with the usual sharing. – 20% of $400 K May 2007 Pixel Electronics --- US ATLAS Upgrade R&D --- Garcia-Sciveres 8

LBNL FE chip Cost breakdown FY 08 -09 May 2007 Pixel Electronics --- US ATLAS Upgrade R&D --- Garcia-Sciveres 9

Chip Requirements Pixel size 50 x 250 mm 2 Bump pad diameter 12 mm Input DC-coupled negative polarity Normal pixel input capacitance range* 300 -500 f. F Long pixel input capacitance range* 450 -700 f. F In-time threshold with 20 ns gate 4000 e Two-hit time resolution 400 ns DC leakage current tolerance 100 n. A Single channel ENC sigma (400 f. F) 300 e Tuned threshold dispersion 100 e Analog supply current/pixel @400 f. F 10 m. A Radiation tolerance 200 MRad Average hit rate 200 MHz/cm 2 Acquisition mode Data driven with time stamp Time stamp precision 8 Readout initiation Trigger command Max. number of continuous triggers 16 Trigger latency 3. 2 ms Single chip data output rate 160 Mb/s * Low value given by planar sensors and high value by 3 D. May 2007 Very difficult. Critical for power distribution and material bits High luminosity and small radius. Wants new ROD Pixel Electronics --- US ATLAS Upgrade R&D --- Garcia-Sciveres 10

ROD development • • • ROD total bandwidth limited by output s-Link at 1. 28 Gb/s. This is only enough for 8 chips at 160 Mb/s each. This would have to fed into the ROD on 32 40 Mb/s inputs. To read out a single R=4 cm layer would need 94 RODs! It would be much cheaper and reliable to build fewer new, faster RODs using modern components • Can keep the basic data flow architecture, but simply implement within new FPGA. • This is NOT yet an urgent need. Could in principle start in FY 09 instead of FY 08, but – There is available manpower in FY 08 – Early design would feed-back into chip I/O architecture, leading to a better system – There is synergy with PLL-based test setup needs May 2007 Pixel Electronics --- US ATLAS Upgrade R&D --- Garcia-Sciveres 11

ROD & PLL test setup • Interface definition is common to ROD and PLL test setup work, and is needed for chip architecture design. • Expertise at LBNL is common to ROD and PLL test setup (same people) • FY 08 Tasks to be covered in the ROD/PLL area are: – Interface definition – Schematic layout of revised PLL test card – Initial look at new generation candidate FPGA for replacement ROD. • FY 08 requested resources (split between chip and ROD) – 0. 2 FTE under 4. 1. 2. 1 – 0. 083 FTE under ROD – 10 K M&S under ROD (Xilinix evaluation boards) • FY 09 requested resources (split between chip and ROD) – 0. 53 FTE under 4. 1. 2. 1 (includes PLL test card layout & fab) – 0. 3 FTE under ROD (prototype BOC and ROD design) – 30 K M&S under 4. 1. 2. 1 (PLL test card fab) May 2007 Pixel Electronics --- US ATLAS Upgrade R&D --- Garcia-Sciveres 12

LBNL ROD Cost breakdown FY 08 -09 May 2007 Pixel Electronics --- US ATLAS Upgrade R&D --- Garcia-Sciveres 13

Other LBNL activities • Progress in FY 07 in – 3 D sensor testing and – Nanowire carpet hybrid pixel development • 3 D sensor testing – Minor involvement but very positive impact • Established characterization setup at CERN enabling test work by U. of Oslo • Provided test boards and debugging help • Results from this work used to specify load requirement on new 130 nm amplifier. – Will need to increase involvement in FY 09 once first 130 nm full chip is available • Note request for “tester” support in FY 09 4. 1. 2. 1. May 2007 Pixel Electronics --- US ATLAS Upgrade R&D --- Garcia-Sciveres 14

Nanowire carpet hybrid pixels W. Kim (molecular foundry), C. Tindall (eng. ), H. Spieler (phys. ), M. Garcia-Sciveres (phys. ), and brand new addition CERN Medipix group Concept shown at UCSC upgrade meeting Nov. 2005 May 2007 Realized implementation Pixel Electronics --- US ATLAS Upgrade R&D --- Garcia-Sciveres 15

Nanowire carpet hybrid pixels (cont. ) • Funding sources so far – – LBNL molecular foundry (FY 06) LBNL LDRD “surplus” (FY 06) ATLAS project R&D 0. 07 FTE (FY 07) No explicit ATLAS R&D request for FY 08 Diode behavior of NW carpet sample fabricated by C. Tindall in FY 07 May 2007 Pixel Electronics --- US ATLAS Upgrade R&D --- Garcia-Sciveres 16