PIC Architecture Background Microprocessor Requires external support hardware

PIC Architecture: Background Microprocessor: ÕRequires ‘external’ support hardware ÕE. g. , External RAM, ROM, Peripherals. Microcontroller: ÕVery little external support hardware. ÕMost RAM, ROM and peripherals on chip. Õ“Computer on a chip”, or “System on chip” (SOC) ÕE. g. , PIC = Peripheral Interface Controller Õ For example, PICs use: – Data memory (RAM): a small number of 8 bit registers – Program memory (ROM): 12 bit, 14 bit or 16 bit wide (in EPROM, FLASH, or ROM)

PIC Architecture: Background PICs and most Harvard chips are “RISC” ÕReduced Instruction Set Computer (RISC) ÕUsed in: SPARC, ALPHA, Atmel AVR, etc. ÕFew instructions (usually < 50) ÕOnly a few addressing modes ÕExecutes 1 instruction in 1 internal clock cycle (Tcyc) ÕExample: PIC 16 CXXX: MOVLW 0 x 55 1100 XX 0101 1 word, 1 cycle

Example PIC: 12 C 508 Block Diagram

The PIC Family: Cores PICs come with 1 of 4 CPU ‘cores’: Õ 12 bit cores with 33 instructions: 12 C 50 x, 16 C 5 x Õ 14 bit cores with 35 instructions: 12 C 67 x, 16 Cxxx Õ 16 bit cores with 58 instructions: 17 C 4 x, 17 C 7 xx Õ‘Enhanced’ 16 bit cores with 77 instructions: 18 Cxxx

The PIC Family: Packages PICs come in a huge variety of packages: 8 pin DIPs, SOICs: 18 pin DIPs, SOICs: 28 pin DIPs, SOICs: 40 pin DIPs, SOICs: 44 - 68 pin PLCCs*: * also TQFPs, etc. 12 C 50 x (12 bit) and 12 C 67 x (14 bit) 16 C 5 X (12 bit), 16 Cxxx (14 bit), 17 C 4 x (16 bit) 16 Cxxx (14 bit), 17 C 4 x / 17 Cxxx (16 bit)

The PIC Family: Speed PICs require a clock to work. Õ Can use crystals, clock oscillators, or even an RC circuit. Õ Some PICs have a built in 4 MHz RC clock – Not very accurate, but requires no external components! Õ Instruction speed = 1/4 clock speed (Tcyc = 4 * Tclk) Õ All PICs can be run from DC to their maximum spec’d speed: 12 C 50 x 12 C 67 x 16 Cxxx 17 C 4 x / 17 C 7 xxx 18 Cxxx 4 MHz 10 MHz 20 MHz 33 MHz 40 MHz

The PIC Family: Program Memory PIC program space is different for each chip. Some examples are: 12 C 508 16 C 71 C 16 F 877 17 C 766 512 12 bit instructions 1024 (1 k) 14 bit instructions 8192 (8 k) 14 bit instructions 16384 (16 k) 16 bit instructions

The PIC Family: Program Memory PICs have two different types of program storage: 1. EPROM (Erasable Programmable Read Only Memory) Õ Needs high voltage from a programmer to program (~13 V) Õ Needs windowed chips and UV light to erase Õ Note: One Time Programmable (OTP) chips are EPROM chips, but with no window! Õ PIC Examples: Any ‘C’ part: 12 C 50 x, 17 C 7 xx, etc.

The PIC Family: Program Memory PICs have two different types of program storage: 2. FLASH Õ Re-writable (even by chip itself) Õ Much faster to develop on! Õ Finite number of writes (~100 k Writes) Õ PIC Examples: Any ‘F’ part: 16 F 84, 16 F 87 x, 18 Fxxx (future)

The PIC Family: Data Memory PICs use general purpose “file registers” for RAM (each register is 8 bits for all PICs) Some examples are: 12 C 508 16 C 71 C 16 F 877 17 C 766 • 25 Bytes RAM 368 Bytes (plus 256 Bytes of nonvolatile EEPROM) 902 Bytes RAM Don’t forget, programs are stored in program space (not in data space), so low RAM values are OK.

The PIC Family: Control Registers PICs use a series of “special function registers” for controlling peripherals and PIC behaviors. Some examples are: STATUS Bank select bits, ALU bits (zero, borrow, carry) INTCON Interrupt control: interrupt enables, flags, etc. TRISTristate control for digital I/O: which pins are ‘floating’ TXREG UART transmit register: the next byte to transmit

The PIC Family: Peripherals Different PICs have different on-board peripherals Some common peripherals are: – – – Tri-state (“floatable”) digital I/O pins Analog to Digital Converters (ADC) (8, 10 and 12 bit, 50 ksps) Serial communications: UART (RS-232 C), SPI, I 2 C, CAN Pulse Width Modulation (PWM) (10 bit) Timers and counters (8 and 16 bit) Watchdog timers, Brown out detect, LCD drivers

PIC Peripherals: Ports (Digital I/O) • All PICs have digital I/O pins, called ‘Ports’ – the 8 pin 12 C 508 has 1 Port with 4 digital I/O pins – the 68 pin 17 C 766 has 9 Ports with 66 digital I/O pins • Ports have 2 control registers – TRISx sets whether each pin is an input or output – PORTx sets their output bit levels • Most pins have 25 m. A source/sink (directly drives LEDs) • WARNING: Other peripherals SHARE pins!

PIC Peripherals: ADCs Only available in 14 bit and 16 bit cores Fs (sample rate) < 54 KHz Most 8 bits, newer PICs have 10 or 12 bits All are +/- 1 LSB and are monotonic Theoretically higher accuracy when PIC is in sleep mode (less digital noise) • Can generate an interrupt on ADC conversion done • Multiplexed 3 (12 C 671) - 12 (17 C 7 xxx) channel input – Must wait Tacq to charge up sampling capacitor (see datasheets) • • •

PIC Peripherals: USART: UART • Serial Communications Peripheral: Universal Synchronous/Asynchronous Receiver/Transmitter • Only available in 14 bit and 16 bit cores • Interrupt on TX buffer empty and RX buffer full • Asynchronous communication: UART (RS-232 C serial) – Can do 300 bps - 115 kbps – 8 or 9 bits, parity, start and stop bits, etc. – Outputs 5 V so you need a RS 232 level converter (e. g. , MAX 232)

PIC Peripherals: USART: USRT • Synchronous communication: i. e. , with clock signal • SPI = Serial Peripheral Interface – – • 3 wire: Data in, Data out, Clock Master/Slave (can have multiple masters) Very high speed (1. 6 Mbps) Full speed simultaneous send and receive (Full duplex) I 2 C = Inter IC – 2 wire: Data and Clock – Master/Slave (Single master only; multiple masters clumsy) – Lots of cheap I 2 C chips available; typically < 100 kbps (For example, 8 pin EEPROM chips, ADC, DACs, etc. )

PIC Peripherals: Timers Available in all PICs. 14+bit cores may generate interrupts on timer overflow. Some 8 bits, some 16 bits, some have prescalers Can use external pins as clock in/clock out (ie, for counting events or using a different Fosc) • Warning: some peripherals share Timer resources • •

PIC Peripherals: CCP Modules • Capture/Compare/PWM (CCP) • 10 bit PWM width within 8 bit PWM period (frequency) – Enhanced 16 bit cores have better bit widths • Frequency/Duty cycle resolution tradeoff – 19. 5 KHz has 10 bit resolution – 40 KHz has 8 bit resolution – 1 MHz has 1 bit resolution (makes a 1 MHz clock!) • Can use PWM to do DAC - See AN 655 • Capture counts external pin changes • Compare will interrupt on when the timer equals the value in a compare register

PIC Peripherals: Misc. • Sleep Mode: PIC shuts down until external interrupt (or internal timer) wakes it up. • Interrupt on pin change: Generate an interrupt when a digital input pin changes state (for example, interrupt on keypress). • Watchdog timer: Resets chip if not cleared before overflow • Brown out detect: Resets chip at a known voltage level • LCD drivers: Drives simple LCD displays • Future: CAN bus, 12 bit ADC, better analog functions • VIRTUAL PERIPHERALS: – Peripherals programmed in software. UARTS, timers, and more can be done in software (but it takes most of the resources of the machine)

Low End: 12 C 508 • • • 8 pin package (DIP, SO) 12 bit core - 33 instructions 1 us instruction time (Tclk = 4 MHz) 512 12 bit program memory 25 8 bit data memory or registers (“File registers”) 2 level hardware stack (no interrupts) 5 GPIO pins, 1 input only (25 m. A source/sink) Features: Internal pullups, wake up on pin change, internal oscillator Peripherals: Timer, Watch Dog Timer $1. 88(1), $1. 25(100), $9. 65(W)

Mid Range: 16 F 876 • • • 28 pin package (DIP, SO) 14 bit core - 35 instructions 200 ns instruction time (Tclk = 20 MHz) 8, 092 14 bit FLASH program memory 368 8 bit data memory or registers (“File registers”) 256 8 bit EEPROM (nonvolatile) data registers 8 level hardware stack (interrupts enabled) 22 GPIO (20 m. A source / 25 m. A 7 sink) Peripherals: 5 ch 10 bit ADC, USART/I 2 C/SPI, 16 bit & 8 bit timers Features: Brown out detect, In-Circuit Debugger (ICD) $11. 00(1), $5. 89(100)

High End: 17 C 766 84 pin PLCC package 16 bit core - 58 instructions 121 ns instruction time (Tclk = 33 MHz) 16, 384 16 bit program memory 902 8 bit data memory or registers 16 level hardware stack (priority interrupts) 66 GPIO (20 m. A source / 35 m. A sink) Features: 8 x 8 multiply, BOD, microprocessor mode Peripherals: – 2 x 16 bit + 2 x 8 bit timer, WDT, 2 x USART, 4 x CCP, – 12 ch 10 bit ADC, • $20. 25(1), $10. 53(100), $18. 38(W) • • •

12 C 508, 16 F 876, 17 C 766 Uses • 12 C 508 – Inexpensive controllers, glue logic, simple tasks – E. g. , quadrature decoding, digital interfacing • 16 F 876 – Multitasking programs, serial communication – E. g. , Cheap data acquisition system and digital I/O system for PC off COM ports, data logging • 17 C 766 – RTOS, low end DSP, communications, big moosey applications – E. g. , FEC converter, Rocket Flight Computer, cheap FFT chip

Instruction Examples movlw 0 x. FF Move (“mov”) the number (“l” for “literal”) 0 x. FF - that’s 256 in decimal- into the working register (“w”). In other words, load W with the value 0 x. FF.

Instruction Examples movwf PORTA Move (“mov”) the working register (“w”) into the file register (“f”) named PORTA. In other words, load the register called PORTA with whatever number is in the W register.

Instruction Examples movf PORTA, W Move (“mov”) the value of the file register (“f”) named PORTA into the working register (“w”). In other words, load W with the whatever number is in PORTA.

Assembly Format • • • First column: Labels Second column: opcodes and assembler directives Third Columns & more: operands ; This is a comments since it starts with a “; ” ; This program puts out a square wave on PORTA Pin 0 Loop clrf bsf nop bcf goto PORTA ; Clear PORTA register TRISA ; Make PORTA all outputs PORTA, 0; Turn on PORTA Pin 0 ; Match ‘goto’ delay ; “ “ “ PORTA, 0; Turn off PORTA Pin 0 Loop ; If not zero, loop back

Branch Instruction • All branches are “Bit Tests” • All branches only skip one instruction ; Set Equal. Flag if PORTA = PORTB bcf movf subwf btfsc bsf Equal. Flag, 7 ; First, clear the flag PORTA, W ; Move PORTA -> W PORTB, W ; W - PORTB -> W STATUS, Z ; Check Z bit (see STATUS) Equal. Flag, 7 ; Ports equal; set flag

STATUS Register

Direct Addressing • All file registers (RAM) are accessed by an address. This is called direct addressing. • For example, movlw movwf 0 x. FF 0 x 06 loads W with FF, and then loads W into GPIO (address 0 x 06). • Thankfully, we can use labels instead of addresses: GPIO movwf equ GPIO 0 x 06

Relative Addressing • PCL = Low byte of the Program Counter • Can be read and written. • Writing to it sets the address of the next instruction to be executed. 12 bit core 14 bit core

Relative Addressing u. Example of Relative Addressing (using a table): ; Here’s a simple lookup table which is called as a ; subroutine. Expects the table offset to be loaded in W. ; An example call looks like this: ; movlw 0 x 04 ; Load W with 4 ; call Table ; Call the table subroutine ; movwf Result ; Store the result from the table Table addwf retlw PCL, W 0 x 00 0 x 23 0 x 33 0 x 88 ; ; Jump to (current PCL) + W Return with 0 x 00 in W Return with 0 x 23 in W etc.

Indirect Addressing 00 h INDF 04 h FSR • Load indirect address into FSR • Reading/Writing to INDF acts on address stored in FSR • Example code to clear 0 x 20 - 7 F: loop 7 Fh Register File movlw movwf 0 x 20 FSR clrf incf btfss goto INDF FSR, 7 loop

Banking RAM in the PICs is banked, especially special function registers. Use the bank select commands to choose the bank. Either: bsf bcf STATUS, RP 0 STATUS, RPO Or use the assembler directive: Banksel <registername>

Software Tips • Destination bit determines W or F for result • Look at data movement and re-structure Example: A + B -> A MOVF ADDWF MOVWF A, W B, W A 3 instructions MOVF ADDWF B, W A, F 2 instructions

Software Tips ; Define variable names (without bothering with ; absolute addresses) CBLOCK 0 x 20 ; Start of data space. Var 1: 1 Var 2: 1 Var 16: 2 ACCL: 1 ACCH: 1 ENDC ; You can always call one thing many names, Grasshopper. ACCA equ ACCL ACCB equ ACCH ; alias ACCL ; alias ACCH

Software Tips ; This routine multiplies W by tmp (8 x 8). Uses ; temporary register Cnt. Dwn and stores 16 bit result ; in ACCH: ACCL. Mult MSum clrf bsf bcf rrf btfsc addwf rrf decfsz goto return ACCL ACCH Cnt. Down, 3 STATUS, C tmp, F STATUS, C ACCH, F ACCL, F Cnt. Down, F MSum ; Cnt. Down -> 8

Software Tips ; Save the current state on interrupt ; (NOTE: _W must map in both Banks - e. g. 7 F/FF) Interrupt movwf swapf bcf movwf. . . swapf movwf swapf retfie _W STATUS, W ; Move STATUS w/o changing it STATUS, RP 0 ; Switch to page 0 _STATUS ; Save old status (swapped) _STATUS, W ; Load old STATUS (& unswap) STATUS ; also restores old page# _W, F _W, W

Pitfalls! • Bit tests will screw you up! Be careful! • For example: movf Register, W btfsc STATUS, Z goto NZero. . Nzero. (WRONG!)

Pitfalls! • For all 12 and 14 bit cores, the working register, “W”, can NOT be addressed. So: swapf W, W will not work! • However, in the 17 CXXX series you CAN address the working register (called WREG).

Pitfalls! • Peripheral Pin sharing Many times pins share functions. E. g. , a GPIO will share a pin with a UART module (say the TX line). You CAN’T use one pin for two functions! You must choose between them. • Peripheral Resource Sharing Some resources require using the same resource. For example, some of the PWM modules use TMR 2, which may also be used in the USART module.

Pitfalls! • Read-Modify-Write problems CAN BE SERIOUS! (Uplink) • BCF/BSF PORTn Does the following: – – Reads in the PORTn byte Clears/sets the bit Write the whole byte back. BUT! If something external pulls a different output pin low or high during the READ, the read in value will not be what you expect - WORSE, the WRITE will permanently change it that way. • Solution: Use Shadowed I/O (Example: set PORTA Bit 0) bsf _PORTA, 0 movf _PORTA, W movwf PORTA

Pitfalls! Make sure you always set the correct BANK bits! bsf clrf bcf STATUS, RP 0 TRISA STATUS, RPO is correct; but if you just do clrf TRISA you’ll actually execute: clrf PORTA

Programming PICs: ICSP • In-Circuit Serial Programmability – Good for commercial design – Available for most PICS – Assemble boards, then program them MCLR/VPP VDD VSS I/O 1 Clock I/O 2 • Vpp = +13 V • Vdd = Operating Vdd • Cons: Requires dual use on ICSP pins VPP PIC 16 CXX PIC 14 CXXX PIC 12 CXXX Data I/O

Home Task 6 LEDs off only three pins! A I/O PICmicro B I/O C I/O 1 5 6 2 3 4 I/O A B C LEDs 1 2 3 4 5 6 0 0 1 Z Z 0 1 0 0 0 1 1 0 0 0 1 Z Z 0 1 1 0 Z Z 1 0 1 0 1 0 0 0 0 1 1 0 0 0 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0