Physical States for Bits Black Box Representations Truth

Physical States for Bits

Black Box Representations

Truth Tables

Basic Logic Gates

NAND and NOR gates

Sum of Products Circuits

Timing Diagrams

Logic Levels for CMOS

The concept of voltagecontrolled resistance

n. MOS transistor

p. MOS transistor

Now we put together n. MOS and p. MOS transistors to create an inverter

Switch Model for CMOS inverter

Logical operation of CMOS inverter

Explanation of 2 -input CMOS NAND gate

Switch Model for NAND realized in CMOS

Explanation of CMOS NOR

CMOS NAND with 3 inputs

Example of realization of large NAND gates in CMOS

Buffers realized in CMOS

AND gate in CMOS

AND-OR-INVERT gate in CMOS

AND-OR-INVERT gate in CMOS

CMOS OR-AND-INVERT

CMOS OR-AND-INVERT

Data Sheets and how to use them

Test Circuits and Waveforms

Input-Output Characteristics

Logic Levels and Noise Margins for CMOS logic family

Resistive Models of Inverters

Resistive model for CMOS LOW output with resistive load

Resistive model. Representations for CMOS HIGH output Black Box with resistive load

Circuit defintions to calculate currents

Output loading specifications

Estimating sink and source currents

CMOS inverters with nonideal input voltages

CMOS with load and Black inverter Box Representations nonideal 1. 5 voltage input

CMOS with load and Black inverter Box Representations nonideal 3. 5 voltage input

What to do with non-used inputs?

Transition times

How to analyze transition times for CMOS output?

Model of HIGH-to-LOW transition

Fall time

Model of a CMOS Low-to-High Transition

Rise time for a LOW-to-HIGH transition of a CMOS Output

Propagation Delays for a CMOS inverter

Worst-Case Timing using logic -level boundary points

Ground bounce in an IC with eight inverters and one ground pin

CMOS transition gate

Two-input multiplexer using CMOS transmission gates

Schmitt-Trigger Inverter

Operation with slowly changing inputs

CMOS three-state buffers

Open-Drain CMOS NAND

Open-Drain CMOS NAND gate driving a load

Rising and Falling transitions of an open-drain CMOS output

Driving a LED with an opendrain output

Driving a LED with standard CMOS output

Eight Open-Drain Outputs driving a bus

Wired-AND function on three open-drain NAND-gate outputs

Two CMOS outputs trying to maintain opposite values on the same line

Four open-drain outputs driving two inputs in Black Box Representations the LOW state

Four open-drain outputs driving two inputs in the HIGH state

Input and output levels for CMOS devices using a 5 V supply

Transfer characteristics of HC and HCT circuits

Speed and power characteristics of CMOS families operating at 5 V

Input specifications for CMOS families with VCC between 4. 5 V and 5. 5 V

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ECL 2 -input OR/NOR

Problems for quizzes

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