Phase Detector Circuits Presented by Ricky Lau Outline

Phase Detector Circuits Presented by: Ricky Lau

Outline w Why this topic? w Common Phase Detectors (PD) in industry w Novel Phase Detector design w Future design challenges of Phase Detectors

Why this topic? w Clock and Data Recovery Systems (CDR) are extensively used in telecommunication and digital systems w Phase Detector is critical to the performance of a CDR system

Linear vs Bang-Bang PD Linear PD Bang-Bang PD Advantages • Small output jitter • Less sensitive to data patterns Disadvantages • Nonlinearity • High output for non-uniform jitter data

Hogge Phase Detector w Static phase error due to CK->Q delay of FF w Low output jitter and retimes data

Alexander Phase Detector w High output jitter w Maintain VCO frequency even when no data transition w Retimes Data

Improved Bang-Bang PD w Large freq steps enhance pull-in range w Small freq steps reduce output jitter w Half-Rate Architecture

Future Challenges w Jitter performance w Pull-in range w Sensitivity to input data patterns w Reliability w Analog vs Digital PD

Questions?

References 1. 2. 3. 4. 5. M. Ramezani, C. A. T. Salama, "An Improved Bang-Bang Phase Detector for Clock and Data Recovery Applications“, ISCAS, Vol. 1, pp. 715 -718, 2001. B. Razavi, “Challenges in the design high-speed clock and data recovery circuits”, IEEE communications Magazine, Vol. 40, Issue 8, pp. 94 -101, Aug. 2002. S. Soliman, F. Yuan, K. Raahemifar, “An overview of design techniques for CMOS phase detectors”, ISCAS, Vol. 5, pp. 26 -29, May 2002. M. Rau, T. Oberst, R. Lares, A. Rothermel, R. Schweer, N. Menoux, “Clock/Data Recovery PLL Using Half-Frequency Clock”, IEEE Journal of Solid-State Circuits, pp. 1156 -1160, 1997. J. Savoj, B. Razavi, “A 10 -Gb/s CMOS Clock and Data Recovery Circuit with a Half Rate Linear Phase Detector, ” IEEE Journal of Solid-State Circuits, Vol. 36, pp. 761 -768, May 2001