Performance Analysis and Technology of 3 D ICs

Performance Analysis and Technology of 3 D ICs Krishna Saraswat Shukri Souri Kaustav Banerjee Pawan Kapur Department of Electrical Engineering Stanford University Stanford, CA 94305 saraswat@stanford. edu Funding sources: DARPA, MARCO Stanford University Krishna Saraswat

Outline • Why 3 -D ICs? – Limits of Cu/low K technology • 3 D IC performance simulation • 3 -D technologies – Seeding crystallization of amorphous Si – Processed wafer bonding • Thermal simulations Stanford University Krishna Saraswat

Introduction: Interconnect Delay Is Increasing l Chip size is continually increasing due to increasing complexity l Device performance is improving but interconnect delay is increasing l Chip sizes today are wire-pitch limited: Size is determined by amount of wiring required Mark Bohr, IEDM Proceedings, 1995 Stanford University Krishna Saraswat

Cu Resistivity: Effect of Line Width Scaling • Effect of Cu diffusion Barrier • Barriers have higher resistivity • Barriers can’t be scaled below a minimum thickness • Effect of Electron Scattering • Reduced mobility as dimensions decrease • Effect of Higher Frequencies • Carriers confined to outer skin increasing resistivity Problem is worse than anticipated in the ITRS 1999 roadmap Stanford University Krishna Saraswat

Cu Resistivity: Barriers Deposition Technology ITRS 1999 Line width (nm) Globel Local 525 250 280 133 95 48 Atomic Layer Deposition (ALD) Ionized PVD Collimated PVD • 5 nm barrier assumed at the thinnest spot • No scattering assumed, I. e. , bulk resistivity Interconnect dimensions scaled according to ITRS 1999 Stanford University Krishna Saraswat

Cu Resistivity: Effect of Electron Scattering Diffuse scattering al oc e, L us Diff al Diffu lob G , e s Elastic 373 K al oc e, L us 273 K Lower mobility Diff bal Diff Glo use, Elastic scattering Elastic • No barrier assumed • Diffuse electron scattering increases resistivity • Lowering temperature has a big effect Stanford University Krishna Saraswat

Fraction of chip area used by repeaters Rent’s exponents As much as 27% of the chip area at 50 nm node is likely to be occupied by repeaters. Stanford University Krishna Saraswat

3 D ICs with Multiple Active Si Layers Motivation • Performance of ICs is limited due to R, L, C of interconnects • Interconnect length and therefore R, L, C can be minimized by stacking active Si layers • Number of horizontal interconnects can be minimized by using vertical interconnects • Disparate technology integration possible, e. g. , memory & logic, optical I/O, etc. Repeaters optical I/O devices Gate n+/p+ VILIC M 4 M 3 M 2 M 1 Gate n+/p+ T 2 Memory Analog M’ 2 M’ 1 Via Gate n+/p+ T 1 Logic Stanford University Krishna Saraswat

Chip Size Device Size Limited PMOS Wire Pitch Limited NMOS • Memory: SRAM, DRAM Stanford University • Logic, e. g. , µ-Processors Krishna Saraswat

Rent’s Rule N gates T = k NP T = # of I/O terminals N = # of gates k = avg. I/O’s per gate P = Rent’s exponent Stanford University Krishna Saraswat

Determination of Wire-length Distribution • Conservation of I/O’s TA + TB + TC = TA-to-B + TA-to-C + TB-to-C + TABC Block A with NA gates TA-to-B = TA + TB -TAB TB-to-C = TB+ TC -TBC Block B • Values of T within a block or collection of blocks are calculated using Rent’s rule, e. g. , TA = k (NA) P TABC = k (NA+ NB+ NC) P • Recursive use of Rent’s rule gives wire-length distribution for the whole chip Block C Ref: Davis & Meindl, IEEE TED, March 1998 Stanford University Krishna Saraswat

Inter-Layer Connections For 3 -D 2 -Layers N N/2 T T 1 T 2 • Fraction of I/O ports T 1 and T 2 is used for inter-layer connections, Tint • Assume I/O port conservation: T = T 1 + T 2 - Tint • Use Rent’s Rule: T = k. NP to solve for Tint (p assumed constant) k = Avg. I/O’s per gate Stanford University N = No. of gates p = Rent’s exponent Krishna Saraswat

Wire-length Distribution of 3 -D IC 1 2 5 3 Single Layer 4 1 5 3 4 Microprocessor Example from NTRS 50 nm Node Number of Gates 180 million Minimum Feature Size 50 nm Number of wiring levels, 9 Metal Resistivity, Copper 1. 673 e-6 Ω-cm Dielectric Constant, Polymer er = 2. 5 2 Layers 2 Replace horizontal by vertical interconnect Vertical inter-layer connections reduce metal wiring requirement Stanford University Krishna Saraswat

Chip Area Estimation • Placement of a wire in a tier is determined by some constraint, e. g. , maximum allowed RC delay • Wiring Area = wire pitch x total length Areq = ploc. Ltot_loc + psemi. Ltot_semi + pglob. Ltot_glob = Aloc + Asemi + Aglob • Ltot calculated from wire-length distribution A 3 -tier wiring network Global Semiglobal Local Stanford University Krishna Saraswat

2 Active Layer Results • Upper tiers pitches are reduced for constant chip frequency, fc • Less wiring needed • Almost 50% reduction in chip area Stanford University Krishna Saraswat

3 -D Wire-Length Distribution Symmetric Interconnects: Comparable inter- and intradevice layer connectivity Asymmetric Interconnects: Negligible inter-device layer connectivity Ref: Rahman & Reif (MIT) N: Number of logic gates, f. o. : fan-out, k and p: Rent’s parameters, Nz: Number of device layers More vertical interconnects required Stanford University Krishna Saraswat

Normalized Interconnect Delay More than 2 active layers 1. 0 0. 95 0. 85 0. 75 0. 65 1 2 3 4 5 No. of Active Layers Stanford University Krishna Saraswat

Delay of Scaled 2 D and 3 D ICs • Moving repeaters to upper active tiers reduces interconnect delay by 9%. 1. 0 Interconnect Delay • 3 D (2 Si layers) shows significant delay reduction (64%). 0. 1 Typical gate Delay Interconnect Delay: 2 D IC with repeaters 3 D IC constant metal layers 3 D IC 2 X metal layers, 5 Si layers 0. 01 0. 001 50 100 150 200 Technology Generation (nm) • Increasing the number of metal levels in 3 D improves interconnect delay by another 40%. • Increasing the number of Si layers to 5 further improves interconnect 250 delay. Simulations assumed state-of-the-art chip at a technology node with data from NTRS Stanford University Krishna Saraswat

3 D Approaches Repeaters or optical I/O devices Gate Wafer Bonding (MIT) n+/p+ VILIC M 4 M 3 M 2 M 1 Gate n+/p+ T 2 Memory or Analog M’ 2 M’ 1 Via Gate n+/p+ T 1 Logic Epitaxial Lateral Overgrowth (Purdue) Stanford University Seeding crystallization of -Si (Stanford) Krishna Saraswat

Statistical Variations in Poly-TFT Properties Conventional Poly-TFT Mobility Grain size 0. 3 -0. 5 µm Effect of Grain Boundaries • As channel length grain size, statistical variation increases • Elimination of grain boundaries should reduce this variation Stanford University Krishna Saraswat

Ge Seeded Lateral Crystallization Ge seeds -Si Seeding Si. O 2 a -Si Grain Substrate Grain Growth Single Grain 0. 1 µm NMOS Lateral crystallization MOSFET Fabrication Gate oxide Source Channel Drain Substrate Concept: – Locally induce nucleation – Grow laterally, inhibiting additional nucleation – Build MOSFET in a single grain Stanford University Krishna Saraswat

Single Grain Transistors in Ge Induced Crystallized Si ID-VG of 0. 1 µm NMOS Mobility SGT Stanford University Krishna Saraswat

Ni Seeded Lateral Crystallization NMOS Ni seed Si. Ge gate Si. O 2 Crystallized Si substrate -Si Tmax = 450ºC • Initially transistor fabricated in -Si • Ni seeding for simultaneous crystallization and dopant activation • Low thermal budget (≤ 450°C) • Devices could be fabricated on top of a metal line Stanford University Krishna Saraswat

Thermal Behavior in 3 D ICs Power Dissipation for 2 D • Energy is dissipated during transistor operation • Heat is conducted through the low thermal conductivity dielectric, Silicon substrate and packaging to heat sink • 1 -D model assumed to calculate die temperature Stanford University Krishna Saraswat

3 D Examples for Thermal Study M 4 Bulk Si n+ n+ M 3 M 6 M 2 M 5 M 1 M 4 Gate p+ p+ T 2 M 3 M’ 2 M’ 1 Gate n+ n+ T 1 Bulk Si • Case A: Heat dissipation is confined to one surface Stanford University T 2 Gate n+ n+ T 1 Bulk Si • Case B: Heat dissipation possible from 2 surfaces. Krishna Saraswat

Die Temperature Simulation Attainable die temperatures for 2 -D and 3 -D ICs at the NTRS based 50 nm node using advanced heat-sinking technologies that would reduce the normalized thermal resistance, R Stanford University Krishna Saraswat

3 D ICs: Implications for Circuit Design • Critical Path Layout: By vertical stacking, the distance between logic blocks on the critical path can be reduced to improve circuit performance. • Integration of disparate technologies is easier • Microprocessor Design: on-chip caches on the second active layer will reduce distance from the logic and computational blocks. • RF and Mixed Signal ICs: Substrate isolation between the digital and RF/analog components can be improved by dividing them among separate active layers ideal for system on a chip design. • Optical I/O can be integrated in the top layer • Repeaters: Chip area can be saved by placing repeaters (~ 10, 000 for high performance circuits) on the higher active layers. • Physical Design and Synthesis: Due to a non-planar target graph (upon which the circuit graph is embedded), placement and routing algorithms, and hence synthesis algorithms and architectural choices, need to be suitably modified. Stanford University Krishna Saraswat

Summary • Cu/low k will not solve the problems of interconnects. • Modeling of interconnect delay shows significant improvement by transitioning from 2 -D to 3 -D ICs. • Seeding and lateral crystallization of amorphous Si is a promising technique to implement 3 -D ICs. • Thermal dissipation in 3 -D ICs may require innovative packaging solutions. Stanford University Krishna Saraswat