PCI Bus Introduction n Intel released PCI Bus
PCI Bus – Introduction n Intel released PCI Bus Specification Ver 1. 0 in 1992 as an alternative to VL-Bus PCI Bus now at Version 3. 0 (April 2004) PCI Bus now controlled by the PCI Special Interests Group (PCI SIG) n n hundreds of members (04/2004: 860) The steering committee includes Intel and AMD, Compaq and Gateway and Peripheral Manufacturers like 3 Com. 19/04/2002 ET 4508_p 10 (KR) 1
PCI Background Why not attach peripherals directly to the CPU Bus i. e. a true local bus? § n n Next Generation Processor would require an updated local bus Bus Loading would limit the ‘local bus’ to ONE device (could be improved upon by using buffers). CPU local bus could not be a separate bus, which could allow device-to-device transfer independently of the CPU. 19/04/2002 ET 4508_p 10 (KR) 2
PCI Ver 2. 1 Features (1) § § Processor Independence Decoupling of processor (Host Bus) and PCI Expansion Bus by means of a Bus Bridge 10 loads approx – but 256 functional devices Speed § § Rev. 2. 0: 0 MHz -> 33 MHz Rev. 2. 1: 0 MHz -> 66 MHz 32 -bit transfers – 133 MB/s at 33 MHz 64 -bit data transfers – 266 MB/s at 33 MHz 19/04/2002 ET 4508_p 10 (KR) 3
PCI Ver 2. 1 Features (2) Supports multiprocessor systems Burst transfers of arbitrary length supported Low Pin count (shared address/data lines) PCI Initiator: 49 Pins PCI Target: 47 Pins Bus Mastering with Arbitration Software Configuration (Pn. P) with config registers § Synchronous Bus § Unique ID Numbers (like EISA/MCA) § § § § 19/04/2002 ET 4508_p 10 (KR) 4
PCI ver 2. 2 Additions n PCI Hot-Plug n n Enables removal or replacement of adapter cards without having to shut down the main system PCI Power Management n n Allows OS to manage power usage of PCI cards Supports ACPI and Microsoft’s On. Now (ACPI=Advanced Configuration and Power Interface) 19/04/2002 ET 4508_p 10 (KR) 5
PCI Bus Block Diagram 19/04/2002 ET 4508_p 10 (KR) 6
PC Architecture: Bus structure 19/04/2002 ET 4508_p 10 (KR) 7
PCI Bus Structure (1) § Strict Decoupling of the Processor and Memory Subsystems (Host) Bus from PCI Bus § Host/PCI Bridge (North Bridge) between Host Bus and PCI Bus – invisible to user § PCI units or devices are called PCI Agents § All PCI Agents are connected to the PCI Bus § PCI Agents should be on the Motherboard where possible – but can also be on an adapter 19/04/2002 ET 4508_p 10 (KR) 8
PCI Bus Structure (2) § Max of 3 Slots provided for PCI units § Originally 2 Slots for Audio and Motion Video § Interface to EISA/MCA Bus is a type of Bus Agent – sometimes called South Bridge § The EISA/ISA Expansion bus can be considered as a type of PCI Agent § PCI Bus can connect up to 10 PCI agents § PCI Bus-to-PCI Bus Bridges are also available 19/04/2002 ET 4508_p 10 (KR) 9
PCI Bridge Block Diagram 19/04/2002 ET 4508_p 10 (KR) 10
PCI Bus Data Transfers (1) 1. Prefetch Buffers are for reads 2. Posting Buffers store writes to post out on the addressed bus later 3. PCI Initiator - Current Bus Master initiates a transfer 4. PCI Target - Slave - addressed by the initiator 5. PCI Agents: Initiator and Target are referred to as Agents 19/04/2002 ET 4508_p 10 (KR) 11
PCI Bus Data Transfers (2) § Multiplexed PCI address/data bus reduces pin count § § § Penalty is more clock cycles per transfer (2 cycles for a write or 3 cycles for a read) First Cycle: Address Phase Second Cycle: Write Data Third Cycle: Read Data At 33 MHz Clock and 32 -bit data bus, maximum single write data rate = 66 MB/s, maximum single read data rate = 44 MB/s 19/04/2002 ET 4508_p 10 (KR) 12
PCI Bus Burst Mode (1) 1. Speeds up data rate further because the address is sent out only once 2. Sender and receiver both increase the addresses internally so they only transfer data – there is no address phase. 3. Any number of transfer cycles can be carried out. 4. Max Data Rate (Burst Mode): 133 MB/s (32 -bit bus, 33 MHz) & 266 MB/s (64 -bit bus, 33 MHz) 19/04/2002 ET 4508_p 10 (KR) 13
PCI Burst Mode (2) § § § Unique Feature: PCI Bridge independently forms burst accesses The PCI Bridge joins together single transfer reads and writes to form burst accesses if the addresses of individual accesses are sequential Can make bursts even if an address is left out of a possible sequence § e. g. DW 0 -DW 1 -DW 3 -DW 4 -DW 5. PCI Bridge performs DW 0 -DW 1 -DW 2 -DW 3 -DW 4 -DW 5 but deasserts all BEX# signals for DW 2 to make sure that no data are actually transferred 19/04/2002 ET 4508_p 10 (KR) 14
PCI Burst Mode (3) 19/04/2002 ET 4508_p 10 (KR) 15
Some PCI Bus Signals (1) n Frame n n AD Bus (I/O) n n Driven by current Initiator, indicates start & duration of a transaction Multiplexed Address and Data Bus signals: can be 32 - or 64 -bits wide. C/BE 3# - C/BE 0# (32 -bit bus) or C/BE 7# C/BE 0# (64 -bit bus) n Bus Command Bus Enable signals are transferred on these pins. During the address phase, C/BE 3# - C/BE 0# indicate the type of bus cycle. 19/04/2002 ET 4508_p 10 (KR) 16
Some PCI Bus Signals (2) n n IRDY#: Initiator RDY signal Low : the Initiator (Bus Master) is ready and can complete the data transfer n n TRDY# Target Data RDY# signal n n n Writes: data is now valid, Reads: initiator can read the data. Low: the addressed PCI unit (target) is ready so current data phase can be completed Only if IRDY# and TRDY# are BOTH active (low) at the same time can the data transfer be completed. DEVSEL#: Device Select n Low indicates that the decode unit has identified a PCI unit as the target of the bus operation 19/04/2002 ET 4508_p 10 (KR) 17
PCI Bus Cycles C/BE 3#C/BE 0# Command C/BE 3# C/BE 0# Command 0000 INTA Sequence 1000 Reserved 0001 Special Cycle 1001 Reserved 0010 I/O Read 1010 Configuration Read 0011 I/O Write 1011 Configuration Write 0100 Reserved 1100 Memory Multiple Access 0101 Reserved 1101 Dual Addressing Cycle 0110 Memory Read 1110 Line Memory Read Access 0111 Memory Write 1111 Memory Write with Invalidation 19/04/2002 ET 4508_p 10 (KR) 18
Bus Arbitration (1) n n PCI Bus Arbitration is performed separately for each access. One Bus Master cannot hold up the bus between two accesses – unlike ISA/EISA/MCA A PCI Burst represents a single arbitration but can extend over many cycles PCI Bus uses Hidden Arbitration to reduce time taken to arbitrate n Arbitration happens “in the background” while data transfers are going on – it’s hidden 19/04/2002 ET 4508_p 10 (KR) 19
Bus Arbitration (2) n n Arbitration signals: REQ# & GNT# Each Bus Master has its own REQ# and GNT# signals (e. g. REQ 0#, GNT 0# etc) – they go to Central Arbitration Logic n n n BM asserts REQ# -> 0: bus master requests the bus Arbitration Logic asserts GNT# -> 0 when it grants the bus Bus master then has 16 CLK cycles to start a transfer, otherwise a timeout will occur 19/04/2002 ET 4508_p 10 (KR) 20
PCI – DMA? n DMA not implemented as such – no DREQ# or DACK# signals n n n Bus Mastering and Bus Arbitration make DMA unnecessary PC/AT: DMA Controller was on the Motherboard and controlled DMA Access from an ISA slot to memory. DMA Controller produced necessary bus control signals. PCI-based system: the bus master on a PCI unit can produce all bus control signals itself and can interface to memory and I/O directly. 19/04/2002 ET 4508_p 10 (KR) 21
PCI – DMA? (2) n DMA n n only arbitration is between CPU and DMA PCI system n n More flexible arbitration between a number of bus masters more complicated scheme 19/04/2002 ET 4508_p 10 (KR) 22
Interrupts (1) n n PCI interrupts are optional – i. e. not essential for each unit PCI interrupts must be active low and level triggered INTA# is assigned to each PCI Unit Only multifunction PCI units can use INTB#, INTC# and INTD# 19/04/2002 ET 4508_p 10 (KR) 23
Interrupts (2) n n n PCI interrupts are formed in the PCI Bridge In PC systems each INTA# interrupt source needs to be associated with IRQ 0 -IRQ 15 for legacy reasons For the PCI bus to function in a PC, the PCI interrupts must be mapped to ISA interrupts But IRQX – INTA# association is done through software, not hardwired as on PC/AT. Pn. P OS (>Windows 95) support PCI IRQ steering (multiple PCI devices share same IRQ) 19/04/2002 ET 4508_p 10 (KR) 24
Interrupts (3) n n ISA Bus needs 11 contacts for interrupt support PCI Bus needs 4 contacts for same functionality 19/04/2002 ET 4508_p 10 (KR) 25
I/O Address Space and the PCI Bus n n n I/O address space is used for PCI registers PC I/O addresses previously left for the Motherboard used for PCI configuration registers. Configuration registers are 32 -bits wide and form a gateway and an enable path to the Configuration Area of PCI devices. n n n CONFIG_ADDRESS: 0 CF 8 h CONFIG_DATA: 0 CFCh These addresses do NOT conflict with any EISA/MCA I/O addresses 19/04/2002 ET 4508_p 10 (KR) 26
Configuring a PCI Unit Three ways of accessing PCI Config area: 1. Use I/O addresses at 0 CF 8 h & 0 CFCh as CONFIG_ADDRESS & CONFIG_DATA 2. Use I/O addresses at 0 CF 8 h & 0 CFAh to map I/O address range 0 C 000 h-0 CFFFh directly onto the PCI Config Area 3. Use BIOS Interrupt INT 1 Ah 19/04/2002 ET 4508_p 10 (KR) 27
PCI CONFIG_ADDRESS The bus field - can have several PCI buses in a hierarchy Bus 0 closest to the CPU. The Unit field selects one of 32 possible PCI agents. The Function Field selects one of 8 functions – if the PCI Unit is a multifunction device The Register Field selects one of 64 possible double word registers (256 bytes) in the Configuration Area. 19/04/2002 ET 4508_p 10 (KR) 28
PCI Configuration Address Space n n n Every PCI Unit and separate function in a multifunction unit has a 256 -byte configuration area Corresponds to 64 x 32 -bit registers First 64 bytes are a Fixed header Area. Remaining 192 bytes are unit specific. 19/04/2002 ET 4508_p 10 (KR) 29
PCI Configuration Area 19/04/2002 ET 4508_p 10 (KR) 30
Basic and Subclass Codes Basic Code Meaning Subcode Meaning 00 h Unit was produced before Class Codes were defined 00 h All previous units except VGA 01 h VGA Controller for Mass Storage 00 h SCSI controller 01 h IDE Controller 02 h Floppy Controller 03 h IPI Controller 80 h Other Controller 01 h 19/04/2002 ET 4508_p 10 (KR) 31
PCI Connector Physical Bus Slot Configurations n n n 5 Volt PCI Cards: 32 bits 5 Volt PCI Cards: 64 bits 3. 3 Volt PCI Cards: 32 bits 3. 3 Volt PCI Cards: 64 bits Universal PCI Cards: 32 bits (5 V & 3. 3 V) Universal PCI Cards: 64 bits (5 V & 3. 3 V) 19/04/2002 ET 4508_p 10 (KR) 32
32 -bit PCI (5 V) 19/04/2002 ET 4508_p 10 (KR) 33
64 -bit PCI 19/04/2002 ET 4508_p 10 (KR) 34
PCI Bus in non-Intel environments 19/04/2002 ET 4508_p 10 (KR) 35
Elimination of ISA Bus n n n ISA Bus is slow, hard to use and bulky Microsoft/Intel PC 1999 and PC 2001 promote the elimination of ISA bus slots from new PC designs ISA plug in cards to be replaced by either PCI plug-in cards or USB add-on peripherals 19/04/2002 ET 4508_p 10 (KR) 36
Mini PCI & PCI-X n Mini (or Small) PCI – small form factor PCI implementation for Laptops & Notebooks n n n Uses keyed PC-Card or Cardbus Connctors Similar Performance to PCI-X: improved data transfer rate PCI-X 64 -bit bus at frequencies up to 133 MHz Theoretically capable of 1 Gbyte/s transfer rate Easier to design than 66 MHz PCI 19/04/2002 ET 4508_p 10 (KR) 37
Future I/O and NGIO n Future I/O: Builds on PCI Standard n n Promoted by Computer Manufacturers Available 2001? Next Generation IO: new serial type standard proposed by Intel & Sun Aims to make Server design more modular n Available 2001/2 ? 19/04/2002 ET 4508_p 10 (KR) 38
Bus Performance A Comparison of Server I/O Architectures Below are four architectures. Some are currently used, others are proposed solutions. PCI-X Future I/O NGIO Clock speed: 33 MHz 133 MHz Not available Throughput: 132 M byte/sec. 1 G byte/sec. 2. 5 G byte/sec. Availability Now End of year 2001 or 2002 Vendor support: Intel Compaq, HP Compaq, and IBM, HP, 3 Com and Adaptec 19/04/2002 ET 4508_p 10 (KR) Intel, Sun 39
Advanced Graphics Port (AGP) n n n Even PCI Bus can become a bottleneck for 3 D Graphics Problem is made worse because many devices can compete for the bus The Accelerated Graphics Port (AGP) interface is a bus specification that enables high performance graphics capabilities, especially 3 D, for PCs 19/04/2002 ET 4508_p 10 (KR) 40
AGP (2) n n n The AGP Port is independent of the PCI bus AGP is an additional connection point in the system AGP is intended exclusively for visual display devices; all other I/O devices will remain on the PCI bus. AGP uses a new connector body which is not compatible with the PCI connector PCI and A. G. P. boards are not mechanically interchangeable. 19/04/2002 ET 4508_p 10 (KR) 41
AGP and PCI 19/04/2002 ET 4508_p 10 (KR) 42
AGP in Multiprocessor Environment 19/04/2002 ET 4508_p 10 (KR) 43
AGP In System n n AGP provides a high speed port to allow movement of data between the PC’s graphics controller and system memory The AGP interface is positioned between the PC's chipset and graphics controller Significantly increases the bandwidth available to a graphics accelerator (current peak bandwidth is 528 MB/s) Future AGP systems should support a peak bandwidth over 1 GB/s 19/04/2002 ET 4508_p 10 (KR) 44
AGP – Fast Lane for Graphics data n n AGP provides a high memory bandwidth "fast lane" for graphics data AGP enables the hardware-accelerated graphics controller to execute texture maps directly from system memory n n instead of caching them in the relatively limited local video memory also helps speed the flow of decoded video from the CPU to the graphics controller 19/04/2002 ET 4508_p 10 (KR) 45
AGP Data Movement Diagram 19/04/2002 ET 4508_p 10 (KR) 46
Data Movement without AGP 19/04/2002 ET 4508_p 10 (KR) 47
Data Movement with AGP 19/04/2002 ET 4508_p 10 (KR) 48
AGP System Benefits n Graphics Controller can use smaller local video memory n n Reduces costs because video memory is dearer than normal system memory. The PCI Bus is relieved of a lot of highspeed graphics data allowing other devices to achieve greater throughput. 19/04/2002 ET 4508_p 10 (KR) 49
AGP Data Transfer n n AGP max data transfer rate: 533 Mbyte/s at 66 MHz Data transferred on both the rising and falling edges of the 66 MHz clock AGP also uses more efficient data transfer modes. 1 Gbyte/s transfers allowed for in the AGP Spec. n Allow four data transfers per 66 MHz clock cycle. 19/04/2002 ET 4508_p 10 (KR) 50
AGP Pipelining n n n AGP overlaps the memory or bus access times for a request ("n") with the issuing of following requests ("n+1". . . "n+2". . . etc. ) In the PCI bus, request "n+1" does not begin until the data transfer of request "n" finishes Both AGP and PCI can "burst" (transfer multiple data items continuously in response to a single request) n n Bursting only partly alleviates the non-pipelined nature of PCI Depth of AGP pipelining is implementation dependent and remains transparent to application software 19/04/2002 ET 4508_p 10 (KR) 51
Memory Latency: AGP vs PCI 19/04/2002 ET 4508_p 10 (KR) 52
AGP Sideband Addressing n AGP used 8 extra "sideband" address lines which allow the graphics controller to issue new addresses and requests simultaneously n Even though data continues to move from previous requests on the main 32 data/address lines. 19/04/2002 ET 4508_p 10 (KR) 53
AGP Memory Mapping n n AGP memory is really dynamically allocated areas of system memory that the graphics controller can access quickly Access speed comes form built-in hardware in the Chipset, which translates addresses n n Allows the graphics controller and its software to see a contiguous space in main memory even though the pages are disjointed Graphics controller can access large data structures (1 Kbyte – 128 Kbyte) as a single entity 19/04/2002 ET 4508_p 10 (KR) 54
AGP Memory Mapping: GART n n Built-in Chipset hardware is called the GART (Graphics Address Remapping Table) For accesses to AGP memory, the graphics controller and CPU use a contiguous aperture of several megabytes The GART translates these to various, possibly disjointed, 4 KByte page addresses in system memory PCI devices that access to the AGP memory aperture (for example, for live video capture) also go through the GART. 19/04/2002 ET 4508_p 10 (KR) 55
Summary: Key benefits of AGP (1) n n Peak bandwidth four-times higher than the PCI bus due to pipelining, sideband addressing, and data transfers that occur on both rising and falling edges of the clock Direct execution of texture maps from system memory. AGP enables high-speed direct access to system memory by the graphics controller, rather than forcing it to pre-load the texture data into local video memory. 19/04/2002 ET 4508_p 10 (KR) 56
Summary: Key benefits of AGP (2) n Less PCI bus congestion n n The PCI bus attaches a wide variety of I/O devices AGP operates concurrently with, and independent from, most transactions on PCI CPU accesses to system memory can proceed concurrently with AGP memory reads by the graphics controller. Improved system concurrency: Pentium II or III processor can perform other activities while the graphics chip is accessing texture data in system memory. 19/04/2002 ET 4508_p 10 (KR) 57
Chipsets n n Central to PCs Chipset is the motherboard Two boards with the same chipset are functionally identical Chipset determines: n n n which type of processor can be used how fast it will run how fast the buses will run speed/type/amount of memory etc 19/04/2002 ET 4508_p 10 (KR) 58
Chipset Evolution n Original PC/XT/AT’s contained n n n n n Clock generator 8284 Bus controller 8288 System timer 8253 Interrupt controller(s) 8259 DMA controller(s) 8237 CMOS RAM/RTC Keyboard controller Lots of discrete glue logic (TTL) to complete the motherboard circuit TOTAL: >100 individual chips 19/04/2002 ET 4508_p 10 (KR) 59
Chipset Evolution n n 1986: “Chips and Technologies Inc. ” introduces revolutionary 82 C 206 n n single chip integrating all functions of the main motherboard chips for AT-compatible systems Processor + 82 C 206 + four other chips (buffers) = Complete motherboard circuit based on it: NEAT (New Enhanced AT) chipset later followed by SCAT (Single Chip AT) 82 C 836 19/04/2002 ET 4508_p 10 (KR) 60
Chipset Evolution n Chipset idea rapidly copied by other chip manufacturers n n >1994: INTEL dominates market for n n n Acer, Erso, Opti, Suntac, Symphony, UMC, VLSI… processors chipsets motherboards …eliminating the delay between introduction of new processors and systems using them Today: Niche markets for Acer, VIA, Si. S 19/04/2002 ET 4508_p 10 (KR) 61
Intel Chipsets n Intel Chipset Model Numbers Chipset 420 xx 430 xx 440 xx 8 xx 450 xx 19/04/2002 Processor Family P 4 (486) P 5 (Pentium) P 6 (PII, PIII, P 4) with hub architecture P 6 Server (Pentium Pro, Xeon) ET 4508_p 10 (KR) 62
Chipset Architectures n Two distinct chipset architectures: n North/South Bridge Architecture (Intel’s earlier chipsets) n n Hub Architecture More recent 800 series chipsets use the hub architecture 19/04/2002 ET 4508_p 10 (KR) 63
North/South Bridge Architecture n North Bridge: Bridge between n n South Bridge: Bridge between n Processor bus (66 -400 MHz) and AGP (66 -533 MHz) / PCI (3366 MHz) PCI (33 -66 MHz) and ISA (8 MHz) normally also contains IDE hard disk controller and USB interfaces Super I/O n n attached to the ISA bus. Contains commonly used peripheral items combined in a single chip may also contain CMOS RAM/Clock, IDE controllers, etc… 19/04/2002 ET 4508_p 10 (KR) 64
Example North/South Bridge Architecture 19/04/2002 ET 4508_p 10 (KR) 65
Hub Architectures n Hub Architecture Blocks: n n n Memory Controller Hub (MCH) or Graphic Memory Controller Hub (GMCH) I/O Controller Hub (ICH) Firmware Hub (FWH) 19/04/2002 ET 4508_p 10 (KR) 66
Advantages Hub Architecture n Faster than North/South Bridge Architecture n n Reduced PCI Loading n n Hub interface (AHA bus) is independent of PCI and does not dissipate PCI bandwidth for chipset or Super I/O traffic. This improves PCI performance. Reduced board wiring n n Hub interface is quad-clocked: 266 MB/s Although twice as fast as PCI, the hub interface is only 8 bits wide and requires only 15 signals to be routed on the motherboard. More economical. Less noise. Faster ATA/IDE and USB interfaces n ATA/IDE and USB traffic bypasses PCI 19/04/2002 ET 4508_p 10 (KR) 67
LPC Bus n ICH provides a low-pin-count (LPC) bus n n n 4 bits wide (only 13 signals total)with a maximum bandwidth of 6. 67 MB/s drastically reduces number of traces on motherboard (compared to 96 traces for ISA) mainly supports FWH and LPC I/O Controller 19/04/2002 ET 4508_p 10 (KR) 68
Intel 815 Chipset n n n Introduced June 2000 Mainstream PC chipsets Integral video upgradable via an AGP 4 x slot Support Celeron, Pentium III, etc. Support PC 133 SDRAM (more affordable than RDRAM) 19/04/2002 ET 4508_p 10 (KR) 69
Intel 815 Chipset n Intel 815 Chipset Features n n n 66/100/133 MHz system bus 266 MB/s hub interface (AHA bus) ATA-100 or ATA-66 (100 MB/s drive performance) PC 100 or PC 133 SDRAM Supports up to 512 MB RAM Integrated Audio-Codec 97 Low-power sleep modes 2. . 4 USB ports LPC Bus Elimination of ISA Bus Integrated AGP 2 x 3 D graphics Integrated Ethernet controller 10/100 Mb/s 19/04/2002 ET 4508_p 10 (KR) 70
Intel D 815 Desktop Board 19/04/2002 ET 4508_p 10 (KR) 71
Motherboard with 440 LX Chipset 19/04/2002 ET 4508_p 10 (KR) 72
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