PAW to ROOT to a high energy vision

PAW to ROOT to … a high energy vision

Front-End Electronics & Data Acquisition RIKEN

OBJECTIVE OF THE MEETING • GET is a relatively unique project in data capture for Nucl. Phys. because: – G : for Generic – Multi national lab collaboration – Multi project application: - • ACTAR, AT-TPC, 2 p-TPC, [SAMURAÏ-TPC], R 3 B-TPC GASPARD(Si), [S 3(Si)] Ø To inform you of what is the GET project. Ø What are the different tasks? Ø What are the schedules ? • Not a question of ‘selling’ the project but a question of your active participation as one of major Nucl. Phys. Lab. Internationally.

Multi-Lab Participation 4 men. years AT-TPC 10 men. years 2 p-TPC 9 men. years S 3 & R 3 B-TPC ACTAR 8 men. years S 3 & ACTAR

An experiment for FEE & DAC Generic (Gas, Solid State, Scintillators …) Scalable (100 – 30, 000 channels) Portable/Integrable ( GANIL, RIKEN, NSCL, GSI …) User Oriented Design Reliable/Future Proofing Archecture & Component Choices & Policy Numeric (Early) Energy/Time/Shape Dynamic range Fast Data Reduction & Collection Adaptive Live Control, Optimisation & Stabilisation. Modular (Electromechanical constrains)

Electronics /DAC TASKS GET • Electo-mechanical Int & Cabeling (ZAP) • Hardware IRFU + * Electronics – As. Ad – ASIC + on Front-end Board – Co. Bo – Concentration Board & Cabeling NSCL – MUTANT & BEM & µTCA – Trigger & Time Stamping • Firmware & Software – – – • • • Data stamping & reduction on Co. Bo Slow Control on Co. Bo Data Acquisition System PC farm Data Formating Electronics Simulation CENBG Detector GANIL NSCL, IRFU GANIL IRFU, GANIL, MSU IRFU Calibration IRFU + * A rel System Security - Cooling & Power & Gas control CENBG ative ly Com System control at a Distance * plete Syste Documentation IRFU+* Deve m lome Managment * Effor nt t

Major consideraton in a design of an instrument Electro-mechanical constrains Electronics • Solid State devices (DSSSD, Planar Ge) – – Medium-to-Large number of channels (500 -10, 000) Vacuum Air interfaces Very-FEE or FEE in Vacuum Self-contained detector+FEE(ADC+FPGA) • GAS devices – Micro-pattern gas detectors – Very large number of channels (10, 000 -…) – Gas Air interfaces • Scintillators – Photodiodes (avalance, …) – PMTs Electronics Detector

Beam and target 1 module 32 modules equipped with 3 layers of silicon and electronics rosierph@ipno. in 2 p 3. fr - 20/10/09

SAMURAÏ TPC Maximising the magnetic volume Phys: - Eo. S , GMR, … DAC

AN EXPERIMENTAL APPROACH TOWARDS FEE & DAC Generic (Gas, Solid State, Scintillators …) xxxxo Scalable (100 – 30, 000 channels) xxxxo Portable/Integrable ( GANIL, RIKEN, NSCL, GSI …) xxxxo User Oriented Design Reliable/Future Proofing (under study) xxxoo Archecture & Component Choices & Policy Numeric (Early) Energy/Time/Shape xxxxo Dynamic range xxxxo Fast Data Reduction & Collection xxxxo Adaptive Live Control, Optimisation & Stabilisation. Modular (Electromechanical constrains) xxxoo

Generic Aspects for Nucl. Phys. a g e t Internal & External PAC & Slow Control Variable Sampling (1 100 MHz) Calibration facility & Low Power Good Resoln & Dynamic Range Gain & Discriminator/ch Numeric Trigger Modes Channels/Asic = 64 DISC AGET DET DET DET ASIC for GET Based on the T 2 K Program Filter Filter Hit Patter Multiplicity DISC DISC Trigger ADC Pipe-Line Analog Memory Soln Emanuel POLLACCO IRFU 2009 RNB 8 May FPGA Memory

Generic Aspects for Nucl. Phys. a g e t AGET Internal & External PAC & Slow Control Variable Sampling (1 100 MHz) Calibration facility & Low Power Good Resoln & Dynamic Range Gain & Discriminator/ch Numeric Trigger Modes Channels/Asic = 64 DISC Ext PAC DET DET DET Filter Filter Hit Patter Multiplicity Filter DET ASIC for GET Based on the T 2 K Program DISC DISC Trigger ADC Pipe-Line Analog Memory Soln Emanuel POLLACCO IRFU 2009 RNB 8 May FPGA Memory

HARP test set-up at CERN (oct 07) SEDI/IRFU Emanuel POLLACCO IRFU 2009 15 Ge. V/c p-Pb (# 20 K events) FE electronics validated on 1728 channels RNB 8 May

Concentration Board PA-72 PA FPGA 4 X 25 Mhz -FADC – 12 bits PA-72 Mem I/V Temp Pulser FPGA Mem FPGA Time-Stamp Zero Suppress Base-Line Ordering Data Filtering TRIGGER Switch Numeric (LE Disc) Level 0 - External Temp Level 1 -Pad hits Multiplicity I/V Level 2 – Event Topology MUTANT PA-72 AGET LVDS PA As. Ad PA-72 PA PA ZAP- ZAP- Time Slice PC Farm Co. Bo 256 Pads Emanuel POLLACCO IRFU 2009 Calculated read pattern FPGA Sparse Channel Read BEM Trigger Selective Read of Capa Array Selective/ Calculated -Read out RNB 8 May Temp I/V BUTIS

2. 5 Gb/s Emanuel POLLACCO IRFU 2009 RNB 8 May

43 2 1 on 40 ASAD boards (4 asics/ASAD) Aget ADC TI ADS 6422 Aget ADC LVDS readout signals @ 150 Mbit/s (ADC 12 bits-25 MHz) + slow control and monitoring bus over 2 meters Gb. E dual star carrier P M M C H 39 3837 Aget Counting Rate Up to 1 KHz Aget D ASA 40 Up to 10240 channels = 160 ASICS D ASA support P M Aget 14 slot µTCA Crate 2 PM, 1 MCH, 10 Co. Bo AMC + 1 MUTANT AMC MUTANT for -MUltiplicity FRU Power supply 10 Gb. E MCH uplink PC farm Gb. E network -Trigger(s) -ANd -Time Multiple fibbers in the same link This module could be in M the acquisition room near BE the pc and the scope or inside the external trigger system (with GMT, CENTRUM, BUTIS…

Global architecture for the full version Front End (3 crates) P M M C H To 40 ASAD boards P M Back End PC farm Master MUTANT BE FRU Ethernet Network Power supply Up to 30720 channels with 480 AGET (asics) on 120 ASAD boards Inter-MUTANT Fast I/O link 10 Gb. E MCH uplink P M M C H To 40 ASAD boards P M M C H P M To 40 ASAD boards FRU Power supply Slave MUTANT M

Use of GET • • • GASPARD – external pac(IPNO) S 3 - Beam Tracking S 3 - Si (DSSSD) – external pac 2 p-TPC, ACTAR, AT-TPC SAMURAI-TPC

PAC: Ortec Standard vs ASIC • ATHED – Noise with 60 p. F & i= namps • 30 ke. V FWHM on 50 Me. V • Threshold: Max Energy 1: 850 • GET – Noise with 50 p. F • 87, 500 e FWHM on 62. 5 e 6 • Threshold: Max Energy 1: 550 • Sampling contribution 1: 1500 (23 ke. V in 50 Me. V) • Ortec 142 A PAC – Noise with 50 p. F • 4 ke. V FWHM on 200 Me. V • Threshold: Max Energy 1: 25000 (X 30 better then ATHED)

Summary for GET - Hard • Generic – – – • External/Internal PA Adjustable Shaping Times & Gain, Sampling Dynamic Range - 1: 550 Scalable: 32 ch to 32, 000 ch Disc/Numeric trigger FPGA based soft reconfugerable Reasonable Through-Put – 1 KHz large events (50% occupancy) 4 Gb/s instant • Portable System – BUTIS, CENTRUM … coupling with Spectrometer, Si … • Nuclear Physics Oriented High turn around time: Set-up Data Taking Analysis Set-up … Slow Control Data Base, Calibration Policies, Data Filtering FEE & Backend – archecture - applicable to multi-use