Part II InstructionSet Architecture June 2005 Computer Architecture

Part II Instruction-Set Architecture June 2005 Computer Architecture, Instruction-Set Architecture 1

II Instruction Set Architecture Introduce machine “words” and its “vocabulary, ” learning: • A simple, yet realistic and useful instruction set • Machine language programs; how they are executed • RISC vs CISC instruction-set design philosophy Topics in This Part Chapter 5 Instructions and Addressing Chapter 6 Procedures and Data Chapter 7 Assembly Language Programs Chapter 8 Instruction Set Variations June 2005 Computer Architecture, Instruction-Set Architecture 2

5 Instructions and Addressing First of two chapters on the instruction set of Mini. MIPS: • Required for hardware concepts in later chapters • Not aiming for proficiency in assembler programming Topics in This Chapter 5. 1 Abstract View of Hardware 5. 2 Instruction Formats 5. 3 Simple Arithmetic / Logic Instructions 5. 4 Load and Store Instructions 5. 5 Jump and Branch Instructions 5. 6 Addressing Modes June 2005 Computer Architecture, Instruction-Set Architecture 3

5. 1 Abstract View of Hardware Figure 5. 1 Memory and processing subsystems for Mini. MIPS. June 2005 Computer Architecture, Instruction-Set Architecture 4

Data Types Byte = 8 bits Halfword = 2 bytes Word = 4 bytes Doubleword = 8 bytes Mini. MIPS registers hold 32 -bit (4 -byte) words. Other common data sizes include byte, halfword, and doubleword. June 2005 Computer Architecture, Instruction-Set Architecture 5

Register Conventions Figure 5. 2 Registers and data sizes in Mini. MIPS. June 2005 Computer Architecture, Instruction-Set Architecture 6

5. 2 Instruction Formats Figure 5. 3 A typical instruction for Mini. MIPS and steps in its execution. June 2005 Computer Architecture, Instruction-Set Architecture 7

Add, Subtract, and Specification of Constants Mini. MIPS add & subtract instructions; e. g. , compute: g = (b + c) (e + f) add sub $t 8, $s 2, $s 3 $t 9, $s 5, $s 6 $s 7, $t 8, $t 9 # put the sum b + c in $t 8 # put the sum e + f in $t 9 # set g to ($t 8) ($t 9) Decimal and hex constants Decimal Hexadecimal 25, 123456, 2873 0 x 59, 0 x 12 b 4 c 6, 0 xffff 0000 Machine instruction typically contains an opcode one or more source operands possibly a destination operand June 2005 Computer Architecture, Instruction-Set Architecture 8

Mini. MIPS Instruction Formats Figure 5. 4 Mini. MIPS instructions come in only three formats: register (R), immediate (I), and jump (J). June 2005 Computer Architecture, Instruction-Set Architecture 9

5. 3 Simple Arithmetic/Logic Instructions Add and subtract already discussed; logical instructions are similar add sub and or xor nor $t 0, $s 0, $s 1 $t 0, $s 1 # # # set set set $t 0 $t 0 to to to ($s 0)+($s 1) ($s 0)-($s 1) ($s 0) ($s 1) (($s 0) ($s 1)) Figure 5. 5 The arithmetic instructions add and sub have a format that is common to all two-operand ALU instructions. For these, the fn field specifies the arithmetic/logic operation to be performed. June 2005 Computer Architecture, Instruction-Set Architecture 10

Arithmetic/Logic with One Immediate Operand An operand in the range [ 32 768, 32 767], or [0 x 0000, 0 xffff], can be specified in the immediate field. addi andi ori xori $t 0, $s 0, 61 $t 0, $s 0, 0 x 00 ff # # set set $t 0 to to ($s 0)+61 ($s 0) 0 x 00 ff For arithmetic instructions, the immediate operand is sign-extended Figure 5. 6 Instructions such as addi allow us to perform an arithmetic or logic operation for which one operand is a small constant. June 2005 Computer Architecture, Instruction-Set Architecture 11

5. 4 Load and Store Instructions Figure 5. 7 Mini. MIPS lw and sw instructions and their memory addressing convention that allows for simple access to array elements via a base address and an offset (offset = 4 i leads us to the ith word). June 2005 Computer Architecture, Instruction-Set Architecture 12

lw, sw, and lui Instructions lw sw $s 3” lui $t 0, 40($s 3) $t 0, A($s 3) # load mem[40+($s 3)] in $t 0 # store ($t 0) in mem[A+($s 3)] # “($s 3)” means “content of $s 0, 61 # The immediate value 61 is # loaded in upper half of $s 0 # with lower 16 b set to 0 s Figure 5. 8 The lui instruction allows us to load an arbitrary 16 -bit value into the upper half of a register while setting its lower half to 0 s. June 2005 Computer Architecture, Instruction-Set Architecture 13

Initializing a Register Example 5. 2 Show each of these bit patterns can be loaded into $s 0: 0010 0001 0000 0011 1101 1111 1111 Solution The first bit pattern has the hex representation: 0 x 2110003 d lui ori $s 0, 0 x 2110 $s 0, 0 x 003 d # put the upper half in $s 0 # put the lower half in $s 0 Same can be done, with immediate values changed to 0 xffff for the second bit pattern. But, the following is simpler and faster: nor June 2005 $s 0, $zero # because (0 0) = 1 Computer Architecture, Instruction-Set Architecture 14

5. 5 Jump and Branch Instructions Unconditional jump and jump through register instructions j jr verify $ra # go to mem loc named “verify” # go to address that is in $ra; # $ra may hold a return address Figure 5. 9 The jump instruction j of Mini. MIPS is a J-type instruction which is shown along with how its effective target address is obtained. The jump register (jr) instruction is R-type, with its specified register often being $ra. June 2005 Computer Architecture, Instruction-Set Architecture 15

Conditional Branch Instructions Conditional branches use PC-relative addressing bltz $s 1, L beq $s 1, $s 2, L bne $s 1, $s 2, L # branch on ($s 1)< 0 # branch on ($s 1)=($s 2) # branch on ($s 1) ($s 2) Figure 5. 10 (part 1) Conditional branch instructions of Mini. MIPS. June 2005 Computer Architecture, Instruction-Set Architecture 16

Comparison Instructions for Conditional Branching slt $s 1, $s 2, $s 3 slti $s 1, $s 2, 61 # # # if ($s 2)<($s 3), set $s 1 to 1 else set $s 1 to 0; often followed by beq/bne if ($s 2)<61, set $s 1 to 1 else set $s 1 to 0 Figure 5. 10 (part 2) Comparison instructions of Mini. MIPS. June 2005 Computer Architecture, Instruction-Set Architecture 17

Examples for Conditional Branching If the branch target is too far to be reachable with a 16 -bit offset (rare occurrence), the assembler automatically replaces the branch instruction beq $s 0, $s 1, L 1 with: bne j L 2: . . . $s 1, $s 2, L 2 L 1 # skip jump if (s 1) (s 2) # goto L 1 if (s 1)=(s 2) Forming if-then constructs; e. g. , if (i == j) x = x + y bne $s 1, $s 2, endif add $t 1, $t 2 endif: . . . # branch on i j # execute the “then” part If the condition were (i < j), we would change the first line to: slt beq June 2005 $t 0, $s 1, $s 2 $t 0, $0, endif # set $t 0 to 1 if i<j # branch if ($t 0)=0; # i. e. , i not< j or i j Computer Architecture, Instruction-Set Architecture 18

Compiling if-then-else Statements Example 5. 3 Show a sequence of Mini. MIPS instructions corresponding to: if (i<=j){x = x+1; z = 1; } else {y = y– 1; z = 2*z} Solution Similar to the “if-then” statement, but we need instructions for the “else” part and a way of skipping the “else” part after the “then” part. slt bne addi j else: addi add endif: . . . June 2005 $t 0, $s 2, $s 1 $t 0, $zero, else $t 1, 1 $t 3, $zero, 1 endif $t 2, -1 $t 3, $t 3 # # # # j<i? (inverse condition) if j<i goto else part begin then part: x = x+1 z = 1 skip the else part begin else part: y = y– 1 z = z+z Computer Architecture, Instruction-Set Architecture 19

5. 6 Addressing Modes Figure 5. 11 Schematic representation of addressing modes in Mini. MIPS. June 2005 Computer Architecture, Instruction-Set Architecture 20

Finding the Maximum Value in a List of Integers Example 5. 5 List A is stored in memory beginning at the address given in $s 1. List length is given in $s 2. Find the largest integer in the list and copy it into $t 0. Solution Scan the list, holding the largest element identified thus far in $t 0. lw addi loop: addi beq add add lw slt beq addi j done: . . . June 2005 $t 0, 0($s 1) $t 1, $zero, 0 $t 1, 1 $t 1, $s 2, done $t 2, $t 1 $t 2, $t 2, $s 1 $t 3, 0($t 2) $t 4, $t 0, $t 3 $t 4, $zero, loop $t 0, $t 3, 0 loop # # # # initialize maximum to A[0] initialize index i to 0 increment index i by 1 if all elements examined, quit compute 2 i in $t 2 compute 4 i in $t 2 form address of A[i] in $t 2 load value of A[i] into $t 3 maximum < A[i]? if not, repeat with no change if so, A[i] is the new maximum change completed; now repeat continuation of the program Computer Architecture, Instruction-Set Architecture 21

The 20 Mini. MIPS Instruction Copy Load upper immediate Instructions Add Covered So Far Subtract Arithmetic Logic Memory access Control transfer Table 5. 1 June 2005 Set less than Add immediate Set less than immediate AND OR XOR NOR AND immediate OR immediate XOR immediate Load word Store word Jump register Branch less than 0 Branch equal Branch not equal Usage lui add sub slt addi slti and or xor nor andi ori xori lw sw j jr bltz beq bne Computer Architecture, Instruction-Set Architecture rt, imm rd, rs, rt rt, rs, imm rd, rs, rt rd, rs, rt rt, rs, imm rt, imm(rs) L rs rs, L rs, rt, L op fn 15 0 0 0 8 10 0 0 12 13 14 35 43 2 0 1 4 5 22 32 34 42 36 37 38 39 8

PCSpim appearance June 2005 Computer Architecture, Instruction-Set Architecture 23