Parity Circuits parity generators parity checkers CET 235

Parity Circuits parity generators, parity checkers CET 235 | Combinatorial Logic II 1

Parity • errors happen! • bit errors can occur when digital data is conveyed from a sender to a receiver • ex: consider a professor sending a final course letter grade of ‘B’ in ASCII (Notes set 2) and an error occurring on bit 2 ‘B’ = 6610 = 4216 = 0100 00102 with bit 2 in error: 0100 01102 = ? ? ? X • parity can help with detecting when errors occur CET 235 | Combinatorial Logic II 2

Parity Bit • an extra bit added to a transmission that can help detect bit corruption errors • two types of parity • odd: total number of 1 s is an odd number (w/ parity) • even: total number of 1 s is even • adding odd parity to the letter grade submission… ‘B’ 010000102 two 1 s, an even number; p-bit must be 1 with odd parity bit added: 0100001012 send these 9 bits CET 235 | Combinatorial Logic II 3

Data Reception with Parity • the receiver would verify odd/even parity including the parity bit as received • discrepancy means a parity error occurred • receiving a transmission with parity error… odd parity with bit 2 error: 0100 011012 • this now has an even number of 1 s parity error • consider an even number of bit errors • so parity is accurate only 50% of the time! CET 235 | Combinatorial Logic II 4

Summing the Ones • done with XOR logic • ‘X’ is the parity bit result summing 10 bits • this would be done by both sender & receiver CET 235 | Combinatorial Logic II 5

Parity IC • 74280 9 -bit Parity Generator/Checker • 9 input bits • both Odd & Even outputs • sender would fix one of the inputs to 0 (ground) • receiver would use all 9 CET 235 | Combinatorial Logic II 6