Parallel Beam Back Projection Implementation Srdjan Coric Miriam

Parallel Beam Back Projection: Implementation Srdjan Coric Miriam Leeser Eric Miller

Outline • Annapolis Wildstar • “Simple Architecture” – algorithm – datapath – Performance – Results • Parallelism extraction • “Advanced Architecture 4 x” – datapath – Performance – Results – Implementation issues • Future directions

Data Flow Sinogram data prefetch Sinogram data address generation Data read Sinogram data retrieval Linear interpolation Data accumulation Data write

Interpolation factor error Corner starting position LUT 1 starting position Critical error-accumulation path LUT 1 quantization error LUT 2 quantization error Bit reduction error LUT 3 quantization error LUT 1: LUT 2: LUT 3: 10 . 1. 2. 5 15 15

“Simple Architecture” Datapath

Performance Results: Software vs. FPGA Hardware A B C D E Software - Floating point - 450 MHz Pentium : ~ 240 s Software - Floating point - 1 GHz Dual Pentium : ~ 94 s Software - Fixed point - 450 MHz Pentium : ~ 50 s Software - Fixed point - 1 GHz Dual Pentium : ~ 28 s Hardware - 50 MHz : ~ 5. 4 s Parameters: 1024 projections 1024 samples per projection 512*512 pixels image 9 -bit sinogram data 3 -bit interpolation factor

Original image Hardware output image Zoom: ~200% Grayscale range < Pixel value range (heart features in focus)

Original image Hardware output image Zoom: ~200% Grayscale range < Pixel value range (lung features in focus)

Original image - Hardware output image

Parallelism Issues Case 1: No parallelism extracted Case 2: Pixel level parallelism extracted Case 3: Projection level parallelism extracted Projections Image columns Image rows V 3 V 1 V 2 T~k 1*V 1 T~k 2 * V 3 T~k 1*V 2 k 1 <k 2, V 2 = V 3 = V 1 /4, T=Execution time Memory bandwidth requirements at 50 MHz (for data accumulation) Case 1: 0. 4 GB/s Case 2: 1. 6 GB/s Case 3: 0. 4 GB/s Memory bandwidth limit 1. 2 GB/s

Advanced Architecture - Data Path projection parallelism extracted Simple Architecture

Performance Results: Software vs. FPGA Hardware A B C D E F Software - Floating point - 450 MHz Pentium : ~ 240 s Software - Floating point - 1 GHz Dual Pentium : ~ 94 s Software - Fixed point - 450 MHz Pentium : ~ 50 s Software - Fixed point - 1 GHz Dual Pentium : ~ 28 s Hardware - 50 MHz : ~ 5. 4 s Hardware (Advanced Architecture) - 50 MHz : ~ 1. 3 s Parameters: 1024 projections 1024 samples per projection 512*512 pixels image 9 -bit sinogram data 3 -bit interpolation factor

Implementation Issues - fanout - prj_num(3) fanout = 1565 ! routing delay = 7. 913 ns (~39. 99%)

Implementation Issues - fanout - odd_2_A_4[4] fanout = 144 !

Memory Bridges Stuff 3 architectures implemented: A “Simple Architecture” = non-parallel (on slide 6) B “Advanced Architecture” = 4 -way parallel (slide 12) C “Bridge Free Advanced Arch” = as B but contains no memory bridges (all design buffers in Block. RAMs) from PCI bus to memory banks required for Host-Memory communication. Bridges are separate design that is downloaded before (after) design C is downloaded so that input data can be stored to (output data read from) memories on the Wild. Star board. Virtex 1000 resource utilization: A 11% logic, 90% Block. RAMs (with bridges) B 39% logic, 100% Block. RAMs C 21% logic, 100% Block. RAMs

Floorplan of the “Bridge Free Advanced Architecture” (design C on the previous slide)

Future Directions • Graduate