Parallel Architectures Memory Consistency Synchronization Figures examples 1
- Slides: 38
Parallel Architectures Memory Consistency + Synchronization • Figures, examples από 1. Transactional Memory, D. Wood, Lecture Notes in ACACES 2009 2. Krste Asanović’s Lecture Notes, University of California, Berkeley. cslab@ntua 2012 -2013 1
Παράδειγμα 2 Producer posting Item x: Load Rtail, (tail) Store (Rtail), x Rtail=Rtail+1 Store (tail), Rtail Το πρόγραμμα είναι γραμμένο με την υπόθεση ότι οι εντολές εκτελούνται σε σειρά. cslab@ntua 2012 -2013 Consumer: Load Rhead, (head) spin: Load Rtail, (tail) if Rhead==Rtail goto spin Load R, (Rhead) Rhead=Rhead+1 Store (head), Rhead consume(R)
Παράδειγμα 2 (2) Producer posting Item x: 1 2 Load Rtail, (tail) Store (Rtail), x Rtail=Rtail+1 Store (tail), Rtail Ο tail pointer μπορεί να ανανεωθεί πριν την εγγραφή του x! Consumer: Load Rhead, (head) spin: Load Rtail, (tail) 3 if Rhead==Rtail goto spin Load R, (Rhead) 4 Rhead=Rhead+1 Store (head), Rhead consume(R) § Ο προγραμματιστής υποθέτει ότι αν η 3 πραγματοποιηθεί μετά τη 2, τότε η 4 πραγματοποιείται μετά την 1. § Προβληματικές ακολουθίες: o 2, 3, 4, 1 o 4, 1, 2, 3 cslab@ntua 2012 -2013
Sequential Consistency § “A multiprocessor is sequentially consistent if the result of any execution is the same as if the operations of all the processors were executed in some sequential order, and the operations of each individual processor occur in this sequence in the order specified by its program. ” [Lamport, 1979] § SC = τυχαία μίξη των (εν σειρά) αναφορών των σειριακών προγραμμάτων στους επεξεργαστές cslab@ntua 2012 -2013
Παράδειγμα 2: Relaxed Consistency με Fences Producer posting Item x: Load Rtail, (tail) Store (Rtail), x Fence. SS Rtail=Rtail+1 Store (tail), Rtail εγγυάται ότι ο tail pointer δε θα ανανεωθεί πριν την εγγραφή του x cslab@ntua 2012 -2013 Consumer: Load Rhead, (head) spin: Load Rtail, (tail) if Rhead==Rtail goto spin Fence. LL Load R, (Rhead) εγγυάται ότι ο R δε Rhead=Rhead+1 θα φορτωθεί πριν Store (head), Rhead την εγγραφή του x consume(R)
Weak Ordering vs Release Consistency WO cslab@ntua 2012 -2013 RC
Παράδειγμα: Sparc V 9 memory fences § #Load § #Store. Load § #Load. Store § #Store § Logical or-ed combinations possible § #XY = “All X operations that appear before the memory fence in program order complete before any Y operations that follow after the memory fence in program order. ” § (+) Ευελιξία όσον αφορά την βέλτιστη εκμετάλλευση του εκάστοτε relaxed consistency model για μέγιστη απόδοση § (-) Προγραμματιστικά δύσκολη + ζητήματα μεταφερσιμότητας ανάμεσα σε διαφορετικά models cslab@ntua 2012 -2013
- Eventual consistency vs strong consistency
- Posix shared memory synchronization
- Shared memory consistency models: a tutorial
- Memory consistency models in distributed systems
- Sequential consistency
- Similar and congruent shapes
- Plane figures
- Start area
- Product architecture
- Database and storage architectures
- Base system architectures
- Switched backbone networks
- Autoencoders
- Scalable internet architectures
- Fundamental and incidental interactions
- Gui architectures
- Database system architectures
- Cdn architectures
- Scalable web architectures
- Two tier architecture of data warehouse
- Isa in computer architecture
- Ecommerce system architecture
- Distributed systems architectures
- Backbone network architectures
- Cache coherence for gpu architectures
- Why systolic architectures
- Define like and unlike parallel forces with examples
- Spreading activation psychology
- Implicit memory
- Long term memory vs short term memory
- Internal memory and external memory
- Primary memory and secondary memory
- Logical address
- Which memory is the actual working memory?
- Page fault
- Virtual memory in memory hierarchy consists of
- Eidetic memory vs iconic memory
- Shared vs distributed memory
- Pram models