Packet Classification on PLUG Architecture NILAY VAISH THAWAN

Packet Classification on PLUG Architecture NILAY VAISH THAWAN KOOBURAT CS/ECE 752 ADVANCE COMPUTER ARCHITECTURE I FALL 2010

Motivation � Routers need packet classification to: Qo. S, Security (Firewall), VPN, and etc. � Traffic volume increase rapidly Traffic volume increasing rapidly � Reported CAGR of 50% during 2006 – 2010 Classifier size also increase � Hardware support TCAM – Fixed latency but high power consumption and cost CPU – Maximum flexibility but with high power consumption Custom logic – Good power efficiency but inflexible

Background: PLUG �Pipelined Look. Up Grid (PLUG) Tiled architecture N cores, M memory, R router � Simple µcores � SRAM memory � Message routing via adjacent tile RISC-like ISA with static scheduling �Data flow programming model Input Code block Message Data Code block Data Output

Background: Effi. Cuts � Decision-tree packet classification algorithm Rule Space Rule A Rule B Rule C Rule D

Background: Effi. Cuts (cont. ) � Efficient memory usage: 855 KB for 10 k rule set X = [0, 1] 2 cuts Y = [0, 3] 4 cuts Node Boundary Packet Y Children Array X 0 1 2 3 4 5 6 7 Index X, Y = (1, 2) = X-offset * (Y-cuts) + Y-offset = 1 x 4+2 =6

Mapping Effi. Cuts to PLUG Input 1 st level page 2 rd level page 3 rd level page 4 th level page Leaf + rule array page Rule array Output

Memory Access Scheduling �Periodic multiple accesses m n m n n m �Complex multiple accesses 0 1 2 3 n m n Memory access Computation

Evaluation � Critical path length. Child code block: 200 instructions (4 memory accesses) Leaf code block: 150 instructions (10 memory access) Power Latency Throughput (Gbps) PLUG 1. 4 W 1. 14 µs 33 Processor 80 W 200 ns – 2 µs 10 FPGA - 88 ns 80 TCAM 3 W 7. 46 ns 45

Questions Q/A