OWL Cooperative Thread Array CTA Aware Scheduling Techniques

OWL: Cooperative Thread Array (CTA) Aware Scheduling Techniques for Improving GPGPU Performance Adwait Jog, Onur Kayiran, Nachiappan CN, Asit Mishra, Mahmut Kandemir, Onur Mutlu, Ravi Iyer, Chita Das

Super Computers Desktops Laptops Smartphones Tablets Gaming Consoles GPUs are everywhere! Source: n. VIDIA

Executive Summary n Limited DRAM bandwidth is a critical performance bottleneck n Thousands of concurrently executing threads on a GPU q q n May not always be enough to hide long memory latencies Access small size caches High cache contention Proposal: A comprehensive scheduling policy, which q Reduces Cache Miss Rates q Improves DRAM Bandwidth q Improves Latency Hiding Capability of GPUs 3

Off-chip Bandwidth is Critical! AVG: 32% 100% 80% 60% Type-1 Applications 55% Type-2 Applications 40% AVG-T 1 0% SAD PVC SSC BFS MUM CFD KMN SCP FWT IIX SPMV JPEG BFSR SC FFT SD 2 WP PVR BP CON AES SD 1 BLK HS SLA DN LPS NN PFN LYTE LUD MM STO CP NQU CUTP HW TPAF 20% GPGPU Applications Percentage of total execution cycles wasted waiting for the data to come back from DRAM 4

Outline n Introduction n Background n CTA-Aware Scheduling Policy q 1. Reduces cache miss rates q 2. Improves DRAM Bandwidth n Evaluation n Results and Conclusions 5

High-Level View of a GPU Threads CTA W W CTA W Scheduler L 1 Caches Warps ALUs Interconnect … … SIMT Cores Cooperative Thread Arrays (CTAs) L 2 cache DRAM 6

CTA-Assignment Policy (Example) Multi-threaded CUDA Kernel CTA-1 CTA-2 SIMT Core-1 CTA-3 Warp Scheduler L 1 Caches ALUs CTA-3 CTA-4 SIMT Core-2 CTA-4 Warp Scheduler L 1 Caches ALUs 7

Warp Scheduling Policy n All launched warps on a SIMT core have equal priority q Round-Robin execution n Problem: Many warps stall at long latency operations roughly at the same time Send Memory Requests CTA CTA W W W W All warps have equal priority All warps compute SIMT Core Stalls All warps have equal priority All warps compute Time 8

Solution Send Memory Requests CTA CTA W W W W SIMT Core Stalls All warps have equal priority All warps compute CTA W W CTA Send Memory Requests W W CTA W W • Form Warp-Groups (Narasiman MICRO’ 11) • CTA-Aware grouping • Group Switch is Round-Robin CTA W W CTA Saved Cycles W W Time 9

Outline n Introduction n Background n CTA-Aware Scheduling Policy "OWL" q 1. Reduces cache miss rates q 2. Improves DRAM bandwidth n Evaluation n Results and Conclusions 10

OWL Philosophy (1) OWL focuses on "one work (group) at a time" 11

OWL Philosophy (1) n What does OWL do? q q n n Selects a group (Finds food) Always prioritizes it (Focuses on food) Group switch is NOT round-robin Benefits: q Lesser Cache Contention q Latency hiding benefits via grouping are still present 12

Objective 1: Improve Cache Hit Rates Data for CTA 1 arrives. No switching. CTA 1 CTA 3 CTA 5 CTA 7 Data for CTA 1 arrives. Switch to CTA 1 CTA 3 C 5 CTA 1 C 5 CTA 7 No Switching: 4 CTAs in Time T T Switching: 3 CTAs in Time T Fewer CTAs accessing the cache concurrently Less cache contention Time 13

Reduction in L 1 Miss Rates Normalized L 1 Miss Rates Round-Robin CTA-Grouping-Prioritization 1. 20 1. 00 0. 80 8% 0. 60 18% 0. 40 0. 20 0. 00 SAD SSC BFS KMN IIX SPMV BFSR n Limited benefits for cache insensitive applications n Additional analysis in the paper. AVG. 14

Outline n Introduction n Background n CTA-Aware Scheduling Policy "OWL" q 1. Reduces cache miss rates q 2. Improves DRAM bandwidth (via enhancing bank-level parallelism and row buffer locality) n Evaluation n Results and Conclusions 15

More Background n Independent execution property of CTAs q CTAs can execute and finish in any order n CTA DRAM Data Layout q Consecutive CTAs (in turn warps) can have good spatial locality q (more details to follow) 16

CTA Data Layout (A Simple Example) Data Matrix A(0, 0) A(0, 1) CTA 1 A(0, 2) A(0, 3) CTA 2 mapped to Bank 1 A(1, 0) A(1, 1) A(1, 2) A(1, 3) mapped to Bank 2 A(2, 0) A(2, 1) A(2, 2) A(2, 3) mapped to Bank 3 CTA 3 A(3, 0) A(3, 1) CTA 4 A(3, 2) A(3, 3) mapped to Bank 4 DRAM Data Layout (Row Major) Bank 1 Bank 2 Bank 3 A(2, 0) A(2, 1) A(2, 2) A(2, 3) Bank 4 Average percentage of consecutive CTAs (out of total CTAs) accessing the same row = 64% A(0, 0) A(0, 1) A(0, 2) A(0, 3) A(1, 0) A(1, 1) A(1, 2) A(1, 3) A(3, 0) A(3, 1) A(3, 2) A(3, 3) : : 17

Implications of high CTA-row sharing SIMT Core-2 SIMT Core-1 CTA-3 CTA-2 CTA-4 W W W W CTA Prioritization Order L 2 Cache Idle Banks Row-1 Row-2 Row-3 Row-4 Bank-1 Bank-2 Bank-3 Bank-4 18

Analogy Which counter will you prefer? THOSE WHO HAVE TIME: STAND IN LINE HERE Counter 1 THOSE WHO DON’T HAVE TIME: STAND IN LINE HERE Counter 2

Which counter will you prefer? THOSE WHO HAVE TIME: STAND IN LINE HERE Counter 1 THOSE WHO DON’T HAVE TIME: STAND IN LINE HERE Counter 2

Lower Row Locality Higher Bank Level Parallelism High Row Locality Low Bank Level Parallelism Bank-1 Bank-2 Row-1 Row-2 Req Req Req

OWL Philosophy (2) n What does OWL do now? q q Intelligently selects a group (Intelligently finds food) Always prioritizes it (Focuses on food) n OWL selects non-consecutive CTAs across cores q Attempts to access as many DRAM banks as possible. n Benefits: q Improves bank level parallelism q Latency hiding and cache hit rates benefits are still preserved 22

Objective 2: Improving Bank Level Parallelism SIMT Core-1 SIMT Core-2 CTA-1 CTA-3 CTA-2 CTA-4 W W W W CTA Prioritization Order L 2 Cache 11% increase in bank-level parallelism Row-1 Row-2 Row-3 Row-4 14%Bank-1 decrease buffer locality Bank-2 in row Bank-3 Bank-4 23

Objective 3: Recovering Row Locality SIMT Core-2 SIMT Core-1 CTA-3 CTA-2 CTA-4 W W W Memory Side Prefetching W W W L 2 Hits! L 2 Cache Row-1 Row-2 Row-3 Row-4 Bank-1 Bank-2 Bank-3 Bank-4 24

Outline n Introduction n Background n CTA-Aware Scheduling Policy "OWL" q 1. Reduces cache miss rates q 2. Improves DRAM bandwidth n Evaluation n Results and Conclusions 25

Evaluation Methodology n Evaluated on GPGPU-Sim, a cycle accurate GPU simulator n Baseline Architecture q q n 28 SIMT cores, 8 memory controllers, mesh connected 1300 MHz, SIMT Width = 8, Max. 1024 threads/core 32 KB L 1 data cache, 8 KB Texture and Constant Caches GDDR 3 800 MHz Applications Considered (in total 38) from: q q Map Reduce Applications Rodinia – Heterogeneous Applications Parboil – Throughput Computing Focused Applications NVIDIA CUDA SDK – GPGPU Applications 26

IPC results (Normalized to Round-Robin) n 11% within Perfect L 2 n More details in the paper 44% AVG - T 1 33% BP WP SD 2 31% FFT SC BFSR JPEG SPMV Perfect-L 2 PVR Objective (1+2+3) IIX FWT SCP KMN CFD MUM BFS SSC PVC 3. 0 2. 6 2. 2 1. 8 1. 4 1. 0 0. 6 Objective (1+2) 25% SAD Normalized IPC Objective 1 27

Conclusions n Many GPGPU applications exhibit sub-par performance, primarily because of limited off-chip DRAM bandwidth n OWL scheduling policy improves – q q q n Latency hiding capability of GPUs (via CTA grouping) Cache hit rates (via CTA prioritization) DRAM bandwidth (via intelligent CTA scheduling and prefetching) 33% average IPC improvement over round-robin warp scheduling policy, across type-1 applications 28

THANKS! QUESTIONS? 29

OWL: Cooperative Thread Array (CTA) Aware Scheduling Techniques for Improving GPGPU Performance Adwait Jog, Onur Kayiran, Nachiappan CN, Asit Mishra, Mahmut Kandemir, Onur Mutlu, Ravi Iyer, Chita Das

Related Work n Warp Scheduling: (Rogers+ MICRO 2012, Gebhart+, ISCA 2011, Narasiman+ MICRO 2011) n DRAM scheduling: (Ausavarungnirun+ ISCA 2012, Lakshminarayana+ CAL 2012, Jeong+ HPCA 2012, Yuan+ MICRO 2009) n GPGPU hardware prefetching: (Lee+, MICRO 2009) 31

Memory Side Prefetching n Prefetch the so-far-unfetched cache lines in an already open row into the L 2 cache, just before it is closed n What to prefetch? q Sequentially prefetches the cache lines that were not accessed by demand requests q Sophisticated schemes are left as future work n When to prefetch? q Opportunsitic in Nature q Option 1: Prefetching stops as soon as demand request comes for another row. (Demands are always critical) q Option 2: Give more time for prefetching, make demands wait if there are not many. (Demands are NOT always critical) 32

CTA row sharing n Our experiment driven study shows that: q q q Across 38 applications studied, the percentage of consecutive CTAs (out of total CTAs) accessing the same row is 64%, averaged across all open rows. Ex: if CTAs 1, 2, 3, 4 all access a single row, the CTA row sharing percentage is 100%. The applications considered include many irregular applications, which do not show high row sharing percentages. 33