Overview Why VLSI n Moores Law n The

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Overview Why VLSI? n Moore’s Law. n The VLSI design process. n These lecture

Overview Why VLSI? n Moore’s Law. n The VLSI design process. n These lecture notes include my annotations, changes and additions. These annotations, changes, and additions marked in red are not in any way endorsed or approved by the author or publisher of the text, Modern VLSI Design/System-on-Chip Design. A. Yavuz Oruc, University of Maryland, College Park, MD 20742 Modern VLSI Design 3 e: Chapter 1 Copyright 1998, 2002 Prentice Hall PTR

Why VLSI? n Integration improves the design and fabrication: – lower parasitics (capacitive charging,

Why VLSI? n Integration improves the design and fabrication: – lower parasitics (capacitive charging, resistive dissipation) = higher speed; – lower power (smaller devices+ less heat dissipation at the interface); – physically smaller. n n Integration reduces manufacturing cost-(almost) no manual assembly. Integration also increases system reliability by reducing component interface and interconnections Modern VLSI Design 3 e: Chapter 1 Copyright 1998, 2002 Prentice Hall PTR

VLSI and you n Microprocessors: – personal computers; – microcontrollers. – Hand-held devices-wireless phones,

VLSI and you n Microprocessors: – personal computers; – microcontrollers. – Hand-held devices-wireless phones, pdas, video cameras, etc… DRAM/SRAM Memory chips n Special-purpose processors. n Modern VLSI Design 3 e: Chapter 1 Copyright 1998, 2002 Prentice Hall PTR

Moore’s Law Gordon Moore: co-founder of Intel n Predicted that number of transistors per

Moore’s Law Gordon Moore: co-founder of Intel n Predicted that number of transistors per chip would grow exponentially (double every 18 months). n Exponential improvement in technology is a natural trend: steam engines, dynamos, automobiles. n Modern VLSI Design 3 e: Chapter 1 Copyright 1998, 2002 Prentice Hall PTR

Moore’s Law(Cont’d) n n n Q(n) = 2 Q(n-1. 5) => Q(n) = 2

Moore’s Law(Cont’d) n n n Q(n) = 2 Q(n-1. 5) => Q(n) = 2 k Q(n-1. 5 k), Q(0) = Q 0 (some initial value at some initial date) => k= n/1. 5 and Q(n) = Q 0 2 n/1. 5 = Q 0 (1. 333)n If we replace 1. 5 by 1 we get a much steeper rise (2 n). (Count doubles every year…) Modern VLSI Design 3 e: Chapter 1 Copyright 1998, 2002 Prentice Hall PTR

Moore’s Law(Cont’d) Modern VLSI Design 3 e: Chapter 1 Copyright 1998, 2002 Prentice Hall

Moore’s Law(Cont’d) Modern VLSI Design 3 e: Chapter 1 Copyright 1998, 2002 Prentice Hall PTR

Moore’s Law(Cont’d) ftp: //download. intel. com/museum/Moores_Law/Printed_Materials/Moores_Law_Backgrounder. pdf For a more complete list of intel

Moore’s Law(Cont’d) ftp: //download. intel. com/museum/Moores_Law/Printed_Materials/Moores_Law_Backgrounder. pdf For a more complete list of intel processors and their features, see http: //en. wikipedia. org/wiki/List_of_Intel_microprocessors Modern VLSI Design 3 e: Chapter 1 Copyright 1998, 2002 Prentice Hall PTR

Moore’s Law(Cont’d) Modern VLSI Design 3 e: Chapter 1 Copyright 1998, 2002 Prentice Hall

Moore’s Law(Cont’d) Modern VLSI Design 3 e: Chapter 1 Copyright 1998, 2002 Prentice Hall PTR

Moore’s Law plot Log # transistors This is a log plot--- Taking the log

Moore’s Law plot Log # transistors This is a log plot--- Taking the log of the formula for Q(n) gives a linear relation between the years and log of number of transistors: Log Q(n) = Log Q 0 + n Log 1. 333 (See slide 5) Modern VLSI Design 3 e: Chapter 1 Copyright 1998, 2002 Prentice Hall PTR

The cost of fabrication Current cost: $2 -3 billion. n Typical fab line occupies

The cost of fabrication Current cost: $2 -3 billion. n Typical fab line occupies about 1 city block, employs a few hundred people. n Most profitable period is first 18 months-2 years. n Modern VLSI Design 3 e: Chapter 1 Copyright 1998, 2002 Prentice Hall PTR

Cost factors in ICs n For large-volume ICs: – packaging is largest cost; –

Cost factors in ICs n For large-volume ICs: – packaging is largest cost; – testing is second-largest cost. n For low-volume ICs, design costs may swamp all manufacturing costs. Modern VLSI Design 3 e: Chapter 1 Copyright 1998, 2002 Prentice Hall PTR

The VLSI design process n n May be part of larger product design. Major

The VLSI design process n n May be part of larger product design. Major levels of abstraction: – specification; (describe functionality) – architecture; (describe functionality with building blocks) – logic design; (convert architecture to logic circuits) – circuit design; (convert logic circuits to transistor circuits) – layout. (lay out the transistor circuits in VLSI) Modern VLSI Design 3 e: Chapter 1 Copyright 1998, 2002 Prentice Hall PTR

Challenges in VLSI design Multiple levels of abstraction: transistors to CPUs. n Multiple and

Challenges in VLSI design Multiple levels of abstraction: transistors to CPUs. n Multiple and conflicting constraints: low cost and high performance are often at odds. n Short design time: Late products are often irrelevant. n Modern VLSI Design 3 e: Chapter 1 Copyright 1998, 2002 Prentice Hall PTR

Dealing with complexity Divide-and-conquer: limit the number of components you deal with at any

Dealing with complexity Divide-and-conquer: limit the number of components you deal with at any one time. n Group several components into larger components: n – transistors form gates; – gates form functional units; – functional units form processing elements; – etc. Modern VLSI Design 3 e: Chapter 1 Copyright 1998, 2002 Prentice Hall PTR

Hierarchical name n Interior view of a component: – components and wires that make

Hierarchical name n Interior view of a component: – components and wires that make it up. n Exterior view of a component = type: – body; – pins. cout a b Modern VLSI Design 3 e: Chapter 1 Full adder sum cin Copyright 1998, 2002 Prentice Hall PTR

Instantiating component types n Each instance has its own name: – add 1 (type

Instantiating component types n Each instance has its own name: – add 1 (type full adder) – add 2 (type full adder). n Each instance is a separate copy of the type: cout Add 1. a a Add 1(Full adder) b Modern VLSI Design 3 e: Chapter 1 Add 2. a sum a Add 2(Full adder) b cin sum cin Copyright 1998, 2002 Prentice Hall PTR

A hierarchical logic design Incomplete--- not enough labels to specify the netlist and component

A hierarchical logic design Incomplete--- not enough labels to specify the netlist and component list on the next slide (Component terminal counts do not appear to match either!) box 1 box 2 x z Modern VLSI Design 3 e: Chapter 1 Copyright 1998, 2002 Prentice Hall PTR

Net lists and component lists n Net list: (list of terminals in a net)

Net lists and component lists n Net list: (list of terminals in a net) net 1: top. in 1. in net 2: i 1. out xxx. B topin 1: top. n 1 xxx. xin 1 topin 2: top. n 2 xxx. xin 2 botin 1: top. n 3 xxx. xin 3 net 3: xxx. out i 2. in outnet: i 2. out top. out Modern VLSI Design 3 e: Chapter 1 n Component list (nets connected to each pin of a component): top: in 1=net 1 n 1=topin 1 n 2=topin 2 n 3=topin 3 out=outnet i 1: in=net 1 out=net 2 xxx: xin 1=topin 1 xin 2=topin 2 xin 3=botin 1 B=net 2 out=net 3 i 2: in=net 3 out=outnet Copyright 1998, 2002 Prentice Hall PTR

A hierarchical logic design p i 1 o 1 i 2 o 1 i

A hierarchical logic design p i 1 o 1 i 2 o 1 i 1 N A o 2 top q o 1 s B o 1 C o 2 t i 2 r Inserted & modified the labels Modern VLSI Design 3 e: Chapter 1 i 1 Copyright 1998, 2002 Prentice Hall PTR

Net lists and component lists Two-level net list: Two-level component list Level-1 has 2

Net lists and component lists Two-level net list: Two-level component list Level-1 has 2 components, top and C, which appear on 6 nets: Level-1 has 2 components, top and C and they are on the following nets: top = net 11, net 12, net 13, net 14, net 15 C= net 15, net 16 net 11: top. p net 12: top. q net 13: top. r net 14: top. s, C. i 1 net 15: top. t C. i 2 net 16: C. o 1 Level-2 has 3 components: A, N and B, which appear on 7 nets Level-2 has 3 components, A, N, and B, and they are on the following nets A = net 21, net 22 B = net 23, net 24, net 25 N = net 26, net 27 net 21: top. p, A. i 1 net 22: top. q, A. o 2 net 23: top. r, B. i 2 net 24: top. s, B. o 1 net 25: top. t, B. o 2 net 26: A. o 1, N. i 1 net 27: B. i 1, N. o 1 Modern VLSI Design 3 e: Chapter 1 Copyright 1998, 2002 Prentice Hall PTR

Component hierarchy top i 1 Modern VLSI Design 3 e: Chapter 1 xxx i

Component hierarchy top i 1 Modern VLSI Design 3 e: Chapter 1 xxx i 2 Copyright 1998, 2002 Prentice Hall PTR

Hierarchical names n Typical hierarchical name: – top/i 1. foo component pin Modern VLSI

Hierarchical names n Typical hierarchical name: – top/i 1. foo component pin Modern VLSI Design 3 e: Chapter 1 Copyright 1998, 2002 Prentice Hall PTR

Layout and its abstractions n Layout for dynamic latch: (Top view) Modern VLSI Design

Layout and its abstractions n Layout for dynamic latch: (Top view) Modern VLSI Design 3 e: Chapter 1 Copyright 1998, 2002 Prentice Hall PTR

Stick diagram Modern VLSI Design 3 e: Chapter 1 Copyright 1998, 2002 Prentice Hall

Stick diagram Modern VLSI Design 3 e: Chapter 1 Copyright 1998, 2002 Prentice Hall PTR

Transistor schematic Modern VLSI Design 3 e: Chapter 1 Copyright 1998, 2002 Prentice Hall

Transistor schematic Modern VLSI Design 3 e: Chapter 1 Copyright 1998, 2002 Prentice Hall PTR

Mixed schematic inverter Modern VLSI Design 3 e: Chapter 1 Copyright 1998, 2002 Prentice

Mixed schematic inverter Modern VLSI Design 3 e: Chapter 1 Copyright 1998, 2002 Prentice Hall PTR

Levels of abstraction Specification: function, cost, etc. n Architecture: large blocks. n Logic: gates

Levels of abstraction Specification: function, cost, etc. n Architecture: large blocks. n Logic: gates + registers. n Circuits: transistor sizes for speed, power. n Layout: determines parasitics. n Modern VLSI Design 3 e: Chapter 1 Copyright 1998, 2002 Prentice Hall PTR

Circuit abstraction n Continuous voltages and time: Modern VLSI Design 3 e: Chapter 1

Circuit abstraction n Continuous voltages and time: Modern VLSI Design 3 e: Chapter 1 Copyright 1998, 2002 Prentice Hall PTR

Digital abstraction n Discrete levels, discrete time: Least significant bit 1+1=2 Modern VLSI Design

Digital abstraction n Discrete levels, discrete time: Least significant bit 1+1=2 Modern VLSI Design 3 e: Chapter 1 Copyright 1998, 2002 Prentice Hall PTR

Register-transfer abstraction n Abstract components, abstract data types: 0010 + 0001 + 0111 0100

Register-transfer abstraction n Abstract components, abstract data types: 0010 + 0001 + 0111 0100 Modern VLSI Design 3 e: Chapter 1 Copyright 1998, 2002 Prentice Hall PTR

Top-down v. s. bottom-up design n Top-down design adds functional detail. – Create lower

Top-down v. s. bottom-up design n Top-down design adds functional detail. – Create lower levels of abstraction from upper levels. Bottom-up design creates abstractions from low-level behavior. n Good design needs both top-down and bottom-up efforts. n Modern VLSI Design 3 e: Chapter 1 Copyright 1998, 2002 Prentice Hall PTR

Design abstractions English Executable program function Sequential machines Logic gates specification behavior Throughput, design

Design abstractions English Executable program function Sequential machines Logic gates specification behavior Throughput, design time registertransfer Function units, clock cycles logic transistors circuit rectangles layout Modern VLSI Design 3 e: Chapter 1 cost Literals, logic depth Nanoseconds power microns Copyright 1998, 2002 Prentice Hall PTR

Design validation Must check at every step that errors haven’t been introduced-the longer an

Design validation Must check at every step that errors haven’t been introduced-the longer an error remains, the more expensive it becomes to remove it. n Forward checking: compare results of lessand more-abstract stages. n Back annotation: copy performance numbers to earlier stages. n Modern VLSI Design 3 e: Chapter 1 Copyright 1998, 2002 Prentice Hall PTR

Manufacturing test Not the same as design validation: just because the design is right

Manufacturing test Not the same as design validation: just because the design is right doesn’t mean that every chip coming off the line will be right. n Must quickly check whether manufacturing defects destroy function of chip. n Must also speed-grade. n Modern VLSI Design 3 e: Chapter 1 Copyright 1998, 2002 Prentice Hall PTR

Homework Set-1 (Due: September 19) Problem 1. 1. At the Intel site, http: //www.

Homework Set-1 (Due: September 19) Problem 1. 1. At the Intel site, http: //www. intel. com/pressroom/kits/quickrefyr. htm, the clock speeds of intel family of microprocessors from 1971 to 2004 are listed. Use this list to fit the clock speeds of Intel microprocessors that were manufactured between 1971 and 2004 by a power function, i. e. , determine the base b in f 0 bn, where f 0 is the clock speed in MHz in 1971 and n denotes a year between 1971 and 2004. if more than one processor is listed within a given month, use the clock speed of the fastest processor. Plot the actual clock speeds v. s. the power function you have derived. Problem 1. 2. Give the net and component lists for the following circuit by clearly marking each of the nets and components. Vd input-1 A D input-2 output B C Vs Modern VLSI Design 3 e: Chapter 1 Vs Copyright 1998, 2002 Prentice Hall PTR