Overview of Processor Techniques A brief look at

Overview of Processor Techniques A brief look at CDA 3101 and CDA 5155

Single Cycle Machine • What we learned over the course of this semester • Each instruction is executed fully before the next instruction can start • Requires the clk to be set to the slowest instruction • Whilst executing instructions, each component will be unused for most of the execution and some may never be used.

Single Cycle Machine

Multi Cycle Machine • Breaks up the data path into stages and saves the results of each stage into special registers • Typical stages: – – – IF (Instruction Fetch) ID (Instruction Decode) EX (Execute) MEM (Memory Access) WB (Write Back) • Clk is set to be the longest stage • Each instruction still executes to completion but now takes an amount of clk cycles equal to the number of stages • Not really any faster than Single Cycle as you still have to wait for the instruction to finish; in fact, it’s a little slower because now you have to save results to registers and the slow stages stall the faster ones • Not ever really used; the ideas quickly turned into ….

Pipelining • Found in most modern processors • Takes the stages idea from multi cycle, but executes a different instruction within each stage – This, in theory, makes pipelining ‘number of stages’ faster than multi cycle or single cycle – In practice, however, various problems crop up

Pipelining

Pipelining • Problems you have to worry about: – Data hazards: Later instructions reading from register/memory values not yet stored – Control hazards: Branch instructions might need to go to a different section of code, yet there will be several instructions in the pipe that are executing that shouldn’t be there • Solutions: – Data hazards: • Do nothing (not a solution) • Stall • Forward – Control hazards: • Do nothing (not a solution) • Flush • Predict (and Flush)

Branch Prediction • Used to lower the amount of flushes the processor has to due in event of a branch • The simplest is to always predict not taken and just fetch the next instruction which is what the processor does in the normal case • More advanced implementations keep a state counter remembering what the result of the previous occurrence of the branch was • The results are stored in a buffer mapping the pc of the branch to the value of taken/not taken and the offset to where the branch instruction branches to • If you want to predict not taken, just fetch the next instruction like always • If you want to predict take, branch to the offset stored within the branch buffer • In the event of a mispredict, just flush, load the proper pc, and update the branch prediction buffer

Cache • Like the branch prediction buffer, but used to increase memory accesses speeds • Stores a copy of a memory value within a smaller memory unit • Since the unit is smaller (and closer) it takes less time to get the value allowing you to decrease the clk even further • Typically, there are multiple layers (e. g. have a 4 MB L 2 cache and a 512 KB L 1 cache), as well as specialized caches (e. g. instruction cache) • Not perfect, if there are lots of misses it will be slower as you have to access L 1 then L 2 and then memory

Cache

More Advanced Techniques • Super scalar – Executes multiple instructions at a time by adding more components – Diminishing returns after 2 (that is the amount of hardware used and heat generated goes up faster than the speed increase) – Commonly, processors use 2, 4, or 8 way scaling – Add on to other designs like single cycle or pipelining

More Advanced Techniques • Vector processors – Used in scientific computing – Executes on arrays of data (e. g. add one array with another and store the results in a third array) – Only refers to register storage and ALU processing, so it can be used with other designs too

More Advanced Techniques • Out of order execution (in order arrival / completion) – Very complicated and not used in processors that care about power consumption / heat – Groups instructions into certain types (e. g. add group, memory group) – Places instructions into wait queues until the operands have been calculated – Executes ready instructions in parallel (adds more dedicated hardware) – Places the results in a larger queue where the instructions come in at – When the lead instruction has fully executed it is removed another instruction is fetched

More Advanced Techniques • Out of order execution (in order arrival / completion)

More Advanced Techniques • Multiprocessing / multicore – Adds small, simple, independent processors within a single physical processor – Allows communication through specialized networks and through the larger cache – Each processor also has it’s own smaller cache levels

Other Processors

Other Processors • Having learnt MIPS, we can learn other major processors. • This is only going to be a cursory glance at some interesting differences of the major processors compared to MIPS

ARM • Advanced RISC Machine • The major processor for mobile and embedded electronics, such as phones and tablets • Features are: simple design, low power, low cost

ARM • One of the most interesting features is the conditional execution. • That is, an instruction will execute if some condition is true, otherwise it will not do anything (turned into a nop).

ARM • A set of flags, showing the relation of two numbers : gt, equal, lt. – cmp Ri, Rj # set the flags depending on the values in Ri and Rj – subgt Ri, Rj # i = i – j if flag is gt – sublt Ri, Rj # i = i – j if flag is lt – bne Label # goto Label if flag is not equal

ARM • How to implement while (i != j) { if (i > j) i -= j; else j -= i; }

ARM • In MIPS, assume i is in $s 0, j in $s 1: Loop: beq $s 0, $s 1, Done slt $t 0, $s 1 beq $t 0, $0, L 1 sub $s 1, $s 0 j Loop L 1: sub $s 0, $s 1 L 2: j Loop

ARM • In ARM, Loop: cmp Ri, Rj subgt Ri, Rj sublt Rj, Ri bne Loop

ARM • Discussion: Given the MIPS hardware setup, can we support conditional execution?

ARM • Another interesting feature is its ability to fold shift instructions into data processing instructions (add, sub, move, etc) • In C: – a += (j << 2); • In MIPS (assuming a in $s 0 and j in $s 1): – sll $t 0, $s 1, 2 – add $s 0, $t 0 • In ARM: – ADD Ra, Rj, LSL #2

Intel Processor

Basic Program Execution Registers • General purpose registers – There are eight registers (note that they are not quite general purpose as some instructions assume certain registers) • Segment registers – They define up to six segment selectors • EIP register – Effective instruction pointer • EFLAGS – Program status and control register 9/27/2007 11: 23: 31 PM week 06 -3. ppt 27

General Purpose and Segment Registers 9/27/2007 11: 23: 32 PM week 06 -3. ppt 28

General Purpose Registers EAX — Accumulator for operands and results data EBX — Pointer to data in the DS segment ECX — Counter for string and loop operations EDX — I/O pointer ESI — Pointer to data in the segment pointed to by the DS register; source pointer for string operations • EDI — Pointer to data (or destination) in the segment pointed to by the ES register; destination pointer for string operations • ESP — Stack pointer (in the SS segment) • EBP — Pointer to data on the stack (in the SS segment) • • • 29

Alternative General Purpose Register Names 30

Segment Registers 31

SIMD • To improve performance, Intel adopted SIMD (single instruction multiple data) instructions. • Streaming SIMD Extensions (SSE) introduced eight 128 -bit data registers (called XMM registers) – In 64 -bit modes, they are available as 16 64 -bit registers – The 128 -bit packed single-precision floating-point data type, which allows four single-precision operations to be performed simultaneously 10/7/2007 9: 37: 48 PM week 07 -1. ppt 32

GCC Inline Assembly • GCC inline assembly allows us to insert inline functions written in assembly – http: //www. ibiblio. org/gferg/ldp/GCC-Inline-Assembly-HOWTO. html – GCC provides the utility to specify input and output operands as C variables – Basic inline – Extended inline assembly 10/7/2007 10: 01: 43 PM week 07 -1. ppt 33

GCC Inline Assembly • A simple example: 10/7/2007 10: 03: 01 PM week 07 -1. ppt 34

Using SSE #define mulfvec 4_SSE(a, b, c) { __asm__ __volatile__ ("movups %1, %%xmm 0 nt" "movups %2, %%xmm 1 nt" "mulps %%xmm 0, %%xmm 1 nt" "movups %%xmm 1, %0 nt" : "=m" (c) : "m" (a), "m" (b)); }

BCM 4306 Wireless Card Processor

A Part of the Code from http: //www. ing. unibs. it/~openfwwf/