OUTLINE 1 SOISOI Pixel 2 SOI Pixel Detector

OUTLINE 1. SOI技術とSOI Pixel 2. SOI Pixel Detectorの開発状況 3. まとめ 2

1. 　SOI技術とSOI Pixel SOI : Silicon-On-Insulator SOI Transistor 3

Bulk and SOI (Silicon On Insulator) Wafer 50 -400 nm circuit m 通常の半導体ウエハー (Bulk Wafer) 20 -200 nm Top Si (SOI Layer) circuit BOX(埋込み酸化膜) Radiation Physical Support Sensor SOI Wafer 6

OKI 0. 2 m FD-SOI Pixel Process 0. 2 m Low-Leakage Fully-Depleted SOI CMOS (OKIセミ) 1 Poly, 4 (5) Metal layers, MIM Capacitor, DMOS option Core (I/O) Voltage = 1. 8 (3. 3) V SOI wafer Diameter: 200 mm , Top Si : Cz, ~18 -cm, p-type, ~40 nm thick Buried Oxide: 200 nm thick Handle wafer: Cz、700 -cm (n-type), 650 m thick Backside Thinned to 260 m, and depositted with Al (200 nm). An example of a SOI Pixel cross section 9

Metal contact & p+ implant 1 st Al Handle Wafer Copyright 2007 Oki Electric Industry Co. , Ltd 10

2. SOI Pixel Detectorの開発状況 12

積分型 Pixel (INTPIX) b線 Size : 14 m x 14 m with CDS circuit 14

CNTPIX 5 Pixel Layout 64 x 64 um 2 ~600 Tr/pix x 72列 x 212行 1千万 Transistor

X-ray Image Position resolution INTPIX 2 (pixel size=20 m x 20 m) slit w=25 m X-ray Test Chart 25 m Slit is well separated. 12. 5 [lp/mm] 16 20 18 18

~8 ke. V X-tay 19

SOI Pixel 3 D bonding Cross Section 22

Supplements 24

INTPIX 2 + Lens 読み出しボード(SEABAS) Ethernet 25

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Threshold Variation Back Gate Effect MOS Tr Copyright 2007 Oki Electric Industry Co. , Ltd Substrate Voltage act as Back Gate, and change transistor threshold. 27

BPW Normal Implantation Buried P-Well (BPW) B (~1 E 12 cm-2) B or P(~5 E 15 cm-2) SOI Si Buried Oxide PSUB BPW • Cut Top Si • High Dose • Keep Top Si • Low Dose • Suppress back gate effect. • Reduce electric field around p+ sensor. • Less electric field in BOX to improve radiation hardness 28

Ids-Vgs Measurement without/with BPW w/o BPW with BPW=0 V NMOS back channel open shift Back gate effect is suppressed by the BPW. 29

UNIBONDTM Process (1995, France LETI) -> SOITEC microbubbles hydrophilic bonding ~500 o. C CMOS (Low R) Sensor (High R) 31