Optimization of Verification Effort using Reusable Sequence Collection

Optimization of Verification Effort using Reusable Sequence Collection Dipesh Handa Gaurav Chugh Gaurav Minda Kumar Rajeev Ranjan

Authors Dipesh Handa : R & D Engineer +91 -11 -49233970 dhanda@synopsys. com Gaurav Minda CAE +91 -11 -49233952 gminda@synopsys. com Gaurav Chugh Manager CAE +91 -11 -49233980 cgaurav@synopsys. com Kumar Rajeev Ranjan CAE +91 -11 -49233955 kranjan@synopsys. com

Agenda • Introduction Ø Reusable sequence collection Ø Guidelines to develop reusable sequences • Use model • Benefits

Reusable Sequence Collection • It is a set of configurable sequences with different level of complexities. • Depending on requirement, user can use different level of sequences. • Different levels can be – Level 0 - Sequences to model functionality check for basic operations Level 1 - Sequences to model functionality check for basic scenarios Level 2 - Sequences to model functionality check for complex scenarios • Level 2 Level 1 Sequence collection should be implemented in layered architecture Level 0 NOTE : Levels may increase as per requirement of complexity. C O M P L E X I T Y

Guidelines : Reusable Sequence Collection Sequence collection should be implemented in layered architecture Level 1 sequences will use Level 0 sequences and Level 2 sequences will use level 1 sequences and so on Level 0 sequences : Model basic scenarios like Single READ, Single WRITE. Ø Identify configurable properties of transaction class and declare them as local properties Ø Configuration mechanism to get value of local properties and assign the local properties to transaction properties Level 1 sequences : Model intermediate scenarios like READ followed by WRITE. Ø Declare local properties in Level 1 sequence to map with the Level 0 sequence properties Ø Configuration mechanism to get value of local properties and assign the local properties to sequence 0 properties

Better Understanding of Implementation and Guidelines Clock MASTER data SLAVE Scenario : Multiple number of Write -> Read operation between Master and Slave Master transaction class : Class master_transaction extends uvm_transaction; Commonly used in all scenarios rand bit [7: 0] address = 8’h 01; rand bit [7: 0] data = 8’h 00; rand bit [1: 0] command; Constraints to provide control on range bit enable; bit reset; constraint valid_cmd { command inside {READ, WRITE}; } constraint valid_data {data inside {[8’h 00: 8’hff]}; } constraint valid_addr {address inside {[8‘h 00, 8’h 04]}; } endclass : master_transaction Out of 5 properties only 2 properties (address and data) can be reused.

Level 0 Sequence for Write and Read transfer Declaration and initialization of Local Class wr/rd_seq_level 0 extends uvm_sequence #(master_transaction) properties of random type rand bit [7: 0] address = 8’h 01; rand bit [7: 0] data = 8’h 00; constraint valid_range {address inside {[8’h 00: 8’h 04]}} // controlled value of local variables ------------Apply constraint on ------------local properties virtual task body(); // getting values in local variables from test case level uvm_config_db#(bit[7: 0]) : : get (null, get_full_name(), ”address” , address); uvm_config_db#(bit[7: 0]) : : get (null, get_full_name(), ”data” , UVM data); Configuration setting to get value from test case `uvm_do_with(req, { req. address == address; level req. data == data; req. command == WRITE/READ; }) // Write transaction Applying local properties as endtask: body constraints to generate transaction endclass : wr_seq_level 0

Level 1 Sequence for multiple Write-Read transaction Class wr_rd_seq_level 1 extends uvm_sequence #(master_transaction) rand int unsigned count = 1; rand bit [7: 0] address = 8’h 01; Local properties of level 1 sequence rand bit [7: 0] data = 8’h 00; constraint valid_range (address inside {[8’h 00: 8’h 04]}; count inside {[0: 10]}; ) // controlled value of local variables ------------wr_seq_level 1 wr; // handle of Level 0 write sequence Handles of level 0 rd_seq_level 1 rd; // handle of Level 0 read sequences ------------virtual task body(); // getting values in local variables from higher level Configuration uvm_config_db#(bit[7: 0]) : : get (null, get_full_name(), ”address” , address); mechanism to get uvm_config_db#(bit[7: 0]) : : get (null, get_full_name(), ”data” , data); the value from test uvm_config_db#(int unsigned) : : get (null, get_full_name(), ”count” , count); case for(int i =0; i<count; i++) // no. of iteration Applying local properties as begin constraints to generate transaction `uvm_do_with(wr, { wr. address == address; wr. data == data; }) // Write transaction `uvm_do_with(rd, { rd. address == address; }) // Read transaction endtask: body Count to generate multiple endclass: wr_rd_seq_level 1 transaction

Test to provide configuration information to sequence Class seq_test extends uvm_test; -----------------------virtual function void build_phase(uvm_phase); Configuration setting to set default sequence on manster sequencer // Apply the master sequence to the master sequencer uvm_config_db#(uvm_object_wrapper): : set(this, "env. master. sequencer. main_phase", "default_sequence", wr_rd_seq_level 1 : : type_id: : get()); // Apply directed values to local variables of sequence uvm_config_db#(int unsigned): : set(this, "env. master. sequencer. wr_rd_seq_level 1", “count", 2); uvm_config_db#(bit [7: 0]): : set(this, "env. master. sequencer. wr_rd_seq_level 1", “address", 8‘h 02); uvm_config_db#(bit [7: 0]): : set(this, "env. master. sequencer. wr_rd_seq_level 1", “data", 8’hff); endfunction: build_phase endclass: seq_test Configuration setting to pass directed value to sequence properties

Captured Configurable Fields from various protocols MIPI CSI 2 AXI ØId ØAddress ØBurst_length ØBurst_size ØBurst_type ØCmd_type ØData ØWrite_strob etc. UART Øcount_packet Ørts_delay Øcts_delay Ødelay_packets Øpayload etc. ØVirtual_channel_id ØNum_data_lines ØNum_embedded_lines ØNum_data_pixels ØNum_embedded_pixels ØNum_frames etc.

Benefits It optimizes the verification process by reducing Ø Number of sequences Ø Time span Ø Manual Efforts Ø Engineering Cost • Comparative Study In Terms of With Reusability Without Reusability Number of Test & Sequences required ~5 Reusable Sequences ~30 Normal Directed Sequences

Abstract As a result of increasing complexity of Designs, majority of verification effort goes into stimulus pattern generation by writing UVM/OVM sequences and tests. Sometimes there is no reuse across common type of sequences which results in code duplication and verification closure time is on higher side This paper showcases the concept of building reusable UVM/OVM sequences which can be used to generate different stimulus patterns by configuring the reusable sequences. Reusability reduces code verification efforts and verification closure time. Code snippet of sample reusable sequences are shown to help verification engineers to apply the same concepts while building the reusable sequences for different protocols like AMBA, UART, MIPI