Ongoing Computer Engineering Research Projects at the Lucian

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Ongoing Computer Engineering Research Projects at the Lucian Blaga University of Sibiu Prof. Lucian

Ongoing Computer Engineering Research Projects at the Lucian Blaga University of Sibiu Prof. Lucian VINTAN, Ph. D-Director Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

The Research Team n n n n Prof. Lucian VINTAN, Ph. D – Research

The Research Team n n n n Prof. Lucian VINTAN, Ph. D – Research Chair Assoc. Prof. Adrian FLOREA, Ph. D Senior Lecturer Daniel MORARIU, Ph. D Senior Lecturer Ion MIRONESCU, Ph. D Lecturer Arpad GELLERT, Ph. D Radu CRETULESCU, Ph. D student Horia CALBOREAN, Ph. D student Ciprian RADU, Ph. D student Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

Computing hardware 14 Intel Compute nodes (2 processor HS 21 blades with quad-core Intel

Computing hardware 14 Intel Compute nodes (2 processor HS 21 blades with quad-core Intel Xeon) 2 Cell Compute nodes (2 processor QS 22 blades with. IBM Power. XCell 8 i Processor ) Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

Our current research topics n n n Anticipatory Techniques in Advanced Processor Architectures An

Our current research topics n n n Anticipatory Techniques in Advanced Processor Architectures An Automatic Design Space Exploration Framework for Multicore Architecture Optimizations Optimizing Application Mapping Algorithms for No. Cs through a Unified Framework Optimal Computer Architecture for CFD calculation Adaptive Meta-classifiers for Text Documents Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

Anticipatory Techniques in Advanced Processor Architectures Prof. Lucian VINTAN, Ph. D Assoc. Prof. Adrian

Anticipatory Techniques in Advanced Processor Architectures Prof. Lucian VINTAN, Ph. D Assoc. Prof. Adrian FLOREA, Ph. D Lecturer Arpad GELLERT, Ph. D Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

Fetch Bottleneck n Fetch Rate is limited by the basic-blocks’ dimension (7 -8 instructions

Fetch Bottleneck n Fetch Rate is limited by the basic-blocks’ dimension (7 -8 instructions in SPEC 2000); Solutions n n n Trace-Cache & Multiple (M-1) Branch Predictors; Branch Prediction increases ILP by predicting branch directions and targets and speculatively processing multiple basic-blocks in parallel; As instruction issue width and the pipeline depth are getting higher, accurate branch prediction becomes more essential. Some Challenges n n Identifying and solving some Difficult-to-Predict Branches (unbiased branches); Helping the computer architect to better understand branches’ predictability and also if the predictor should be improved related to Difficult-to-Predict Branches. Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

Difficult to predict unbiased branches n A difficult-to-predict branch in a certain dynamic context

Difficult to predict unbiased branches n A difficult-to-predict branch in a certain dynamic context q unbiased q „highly shuffled“. Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

Predicting Unbiased Branches State of the art branch predictors are unable to accurately predict

Predicting Unbiased Branches State of the art branch predictors are unable to accurately predict unbiased branches; The problem: n Finding new relevant information that could reduce their entropy instead of developing new predictors; Challenge: n Adequately representing unbiased branches in the feature space! n Accurately Predicting Unbiased Branches is still an Open Problem! n Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

Random Degree Metrics Based on: n Hidden Markov Model (HMM) – a strong method

Random Degree Metrics Based on: n Hidden Markov Model (HMM) – a strong method to evaluate the predictability of the sequences generated by unbiased branches; n Discrete entropy of the sequences generated by unbiased branches; n Compression rate (Gzip, Huffman) of the sequences generated by unbiased branches. Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

Issue Bottleneck (Data-flow) Conventional processing models are limited in their processing speed by the

Issue Bottleneck (Data-flow) Conventional processing models are limited in their processing speed by the dynamic program’s critical path (Amdahl); 2 Solutions n Dynamic Instruction Reuse (DIR) is a non-speculative technique. n Value Prediction (VP) is a speculative technique. Common issue n Value locality Chalenges n n n Selective Instruction Reuse (MUL & DIV) Selective Load Value Prediction (“Critical Loads”) Exploiting Selective Instruction Reuse and Value Prediction in a Superscalar / Simultaneous Multithreaded (SMT) Architecture to anticipate Long-Latency Instructions Results Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

Exploiting Selective Instruction Reuse and Value Prediction in a Superscalar Architecture Selective Instruction Reuse

Exploiting Selective Instruction Reuse and Value Prediction in a Superscalar Architecture Selective Instruction Reuse (MUL & DIV) Selective Load Value Prediction (Critical Loads) Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

Selective Instruction Reuse and Value Prediction in Simultaneous Multithreaded Architectures SMT Architecture (M-Sim) enhanced

Selective Instruction Reuse and Value Prediction in Simultaneous Multithreaded Architectures SMT Architecture (M-Sim) enhanced with per Thread RB and LVPT Structures Physical Register File Branch Predictor PC Fetch Unit I-Cache Decode Rename Table Issue Queue Functional Units ROB LSQ RB D-Cache LVPT Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

Exploiting Selective Instruction Reuse and Value Prediction in a Superscalar Architecture The M-SIM Simulator

Exploiting Selective Instruction Reuse and Value Prediction in a Superscalar Architecture The M-SIM Simulator Hardware Configuration Cycle-Level Performance Simulator SPEC Benchmark Power Models Hardware Access Counts n n n Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php Power Estimation Performance Estimation

Exploiting Selective Instruction Reuse and Value Prediction in a Superscalar Architecture Relative IPC speedup

Exploiting Selective Instruction Reuse and Value Prediction in a Superscalar Architecture Relative IPC speedup and relative energy-delay product gain with a Reuse Buffer of 1024 entries, the Trivial Operation Detector, and the Load Value Predictor Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

Conclusions and Further Work n n Indexing the SLVP table with the memory address

Conclusions and Further Work n n Indexing the SLVP table with the memory address instead of the instruction address (PC); Exploiting an N-value locality instead of 1 -value locality; Generating thermal maps for the optimal superscalar and SMT configurations (and, if necessary, developing a run-time thermal manager); Understanding and exploiting instruction reuse and value prediction benefits in a multicore architecture. Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

Anticipatory multicore architectures n Anticipatory multicores would significantly reduce the pressure on the interconnection

Anticipatory multicore architectures n Anticipatory multicores would significantly reduce the pressure on the interconnection network performance/energy; n Value prediction, multithreading and the cache coherence/consistence mechanisms there are subtle, not wellunderstood relationships; n data consistency errors consistency violation detection and recovery; n The inconsistency cause: VP might execute out of order some dependent instructions; n Dynamic Instruction Reuse in a multicore system. Reuse Buffers coherence problems cache coherence mechanisms n Details at http: //webspace. ulbsibiu. ro/lucian. vintan/html/#11 Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

An Automatic Design Space Exploration Framework for Multicore Architecture Optimizations Horia CALBOREAN, Ph. D

An Automatic Design Space Exploration Framework for Multicore Architecture Optimizations Horia CALBOREAN, Ph. D student Prof. Lucian VINTAN, Ph. D Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

Multiobjective optimization Number of (heterogeneous) cores in the processor becomes higher – the systems

Multiobjective optimization Number of (heterogeneous) cores in the processor becomes higher – the systems become more and more complex n More configurations have to be simulated (NP-hard problem) n Time needed to simulate all configurations prohibitive n Performance evaluation has become a multiobjective evaluation n Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

Solutions n Reducing simulation time q q n parallel & distributed simulation sampling simulation

Solutions n Reducing simulation time q q n parallel & distributed simulation sampling simulation Reducing number of simulations q intelligent multiobjective algorithms Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

Proposed framework n n n We developed FADSE (framework for automatic design space exploration)

Proposed framework n n n We developed FADSE (framework for automatic design space exploration) Compatible with most of the existing simulators Portable - implemented in java Includes many well known multiobjective algorithms Is able to run simulators and also well known test problems Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

Existing tools n n n Bounded to a certain simulator (Magellan) Lack portability -

Existing tools n n n Bounded to a certain simulator (Magellan) Lack portability - bounded to a certain operating system (M 3 Explorer, Magellan) Perform design space exploration of small parts of the system (only the cache - Archexplorer) Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

FADSE – application architecture Advanced Computer Architecture & Processing Systems Research Lab http: //acaps.

FADSE – application architecture Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

Features n n n Parallel simulation (client server model) Ability to introduce constrains through

Features n n n Parallel simulation (client server model) Ability to introduce constrains through XML interface Easily configurable through XML files: q q q change DSE algorithm, specify input parameters and their possible values, specify desired output metrics, etc. Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

Our target n n n Perform an evaluation of the existing algorithms on different

Our target n n n Perform an evaluation of the existing algorithms on different simulators Find out which one performs best Improve the algorithms - map them on the specific problem of design space exploration Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

Conclusions n n We have developed a framework which is able to perform automatic

Conclusions n n We have developed a framework which is able to perform automatic design space exploration Extensible, portable Many implemented multiobjective algorithms (through the use of j. Metal) Reduces time through parallel &distributed execution of simulators Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

Optimizing Application Mapping Algorithms for No. Cs through a Unified Framework Ciprian RADU, Ph.

Optimizing Application Mapping Algorithms for No. Cs through a Unified Framework Ciprian RADU, Ph. D student Prof. Lucian VINTAN, Ph. D Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

Outline n Introduction q q n Evaluating application mapping algorithms for Networkson-Chip q q

Outline n Introduction q q n Evaluating application mapping algorithms for Networkson-Chip q q n The application mapping problem for No. Cs The relation between application mapping and routing The framework design The ns-3 No. C simulator Automatic Design Space Exploration for Networks-on. Chip q The framework Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

The application mapping problem for No. Cs Advanced Computer Architecture & Processing Systems Research

The application mapping problem for No. Cs Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

Application mapping & routing Advanced Computer Architecture & Processing Systems Research Lab http: //acaps.

Application mapping & routing Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

Evaluating application mapping algorithms for Networks-on-Chip n Existing application mapping algorithms are currently evaluated

Evaluating application mapping algorithms for Networks-on-Chip n Existing application mapping algorithms are currently evaluated on specific No. Cs q n n e. g. : No. Cs with 2 D mesh topology Existing comparisons between the algorithms are not made on the same No. C architecture We propose a unified framework for the evaluation and optimization of application mapping algorithms on different No. C designs Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

The framework design n 3 major components: q q q A module that contains

The framework design n 3 major components: q q q A module that contains the implementation of different application mapping algorithms; A network traffic generator; A Network-on-Chip simulator. Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

The framework design flow Advanced Computer Architecture & Processing Systems Research Lab http: //acaps.

The framework design flow Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

The ns-3 No. C simulator n n Based on ns-3, an event driven simulator

The ns-3 No. C simulator n n Based on ns-3, an event driven simulator for Internet systems Aims for a good accuracy – speed trade-off Flexible and scalable Current parameters: q q q q Packet size, packet injection rate, packet injection probability; Buffer size; Network size; Switching mechanism (SAF, VCT, Wormhole); Routing protocol (XY, YX, SLB, SO); Network topology (2 D mesh, Irvine mesh); Traffic patterns (bit-complement, bit-reverse, matrix transpose, uniform random). Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

Automatic Design Space Exploration for Networks-on-Chip n Motivation q q n n There is

Automatic Design Space Exploration for Networks-on-Chip n Motivation q q n n There is no No. C suitable for all kinds of workload There is an exponential number of possible No. C architectures Exhaustive DSE is no longer suitable Automatic DSE uses an heuristic driven exploration of the design space q q Disadvantage: near-optimal solutions Advantage: speed Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

The framework Design Space Exploration module n q n DSE module No. C simulator

The framework Design Space Exploration module n q n DSE module No. C simulator Simulation results The DSE module determines the parameters of the No. C architecture q n Network-on-Chip simulator Components: q n Configure the simulator Uses algorithms from Artificial Intelligence The No. C simulator (ns-3 No. C) is automatically configured to simulate the network architecture determined by the DSE module The simulation results (network performance) help the DSE module at generating a better No. C architecture Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

Optimal computer architecture for CFD calculation Senior Lecturer Ion Dan MIRONESCU, Ph. D Prof.

Optimal computer architecture for CFD calculation Senior Lecturer Ion Dan MIRONESCU, Ph. D Prof. Lucian VINTAN, Ph. D Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

Practical aplication n Modelling and simulation of multiscale, multicomponent, multiphase flow in complex geometry

Practical aplication n Modelling and simulation of multiscale, multicomponent, multiphase flow in complex geometry (ongoing projects) for : q q optimisation of sugar crystalisation prediction of the flow properties of polymer based dispers systems (starch and starch fractions, microbial polysacharides) HPC/CFD Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

Goals n n Speed-up of this application on the given architecture Finding the optimal

Goals n n Speed-up of this application on the given architecture Finding the optimal manycore architecture for CFD application (e. g. No. C) Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

Method - Lattice Boltzmann (Chirila, 2010) Advanced Computer Architecture & Processing Systems Research Lab

Method - Lattice Boltzmann (Chirila, 2010) Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

Method advantages n n easy discretization of complex geometry easy incorporation of “multi” models

Method advantages n n easy discretization of complex geometry easy incorporation of “multi” models easy paralelisation easy cupling to other scale models (Molecular Dynamics) Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

COMPUTE EXCHANGE COMPUTE COMPUTE Lo Va ca lu l es Ghost data Computational model

COMPUTE EXCHANGE COMPUTE COMPUTE Lo Va ca lu l es Ghost data Computational model COMPUTE Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

General-purpose manycore platform What can be used and what must be accounted for: n

General-purpose manycore platform What can be used and what must be accounted for: n ILP (super scalar, out of order, branch prediction) n Task and Thread LP (multicore/multiprocessor) n Mixed programming model (shared memory on blade, message passing between blades) n Cache system Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

Special purpose many core platform What can be used and what must be accounted

Special purpose many core platform What can be used and what must be accounted for: n SIMD n Task and Thread LP (hardware multithreading, multicore/multiprocessor) n Message passing n Local store model –full user control Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

Charm++ n n n provides a high-level abstraction of a parallel program cooperating message-driven

Charm++ n n n provides a high-level abstraction of a parallel program cooperating message-driven objects called chares support for load balancing, fault tolerance, automatic checkpointing support for all architectures trough a specific low level tier NAMD MD implementd in charm++ Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

Charm++ LB implementation Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu.

Charm++ LB implementation Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

Charm++ LB implementation Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu.

Charm++ LB implementation Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

DSE Search optimal values for n sites/bloc n blocs (chares)/core, /thread, /blade n communication

DSE Search optimal values for n sites/bloc n blocs (chares)/core, /thread, /blade n communication patterns Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

 Adaptive Meta-classifiers for Text Documents Prof. Lucian VINTAN, Ph. D Daniel MORARIU, Ph.

Adaptive Meta-classifiers for Text Documents Prof. Lucian VINTAN, Ph. D Daniel MORARIU, Ph. D Radu CRETULESCU, Ph. D student Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

Introduction n We investigated a way to create a new adaptive meta-classifier for classifying

Introduction n We investigated a way to create a new adaptive meta-classifier for classifying text documents in order to increase the classification accuracy. During the first processing phase (preclassification) the meta-classifier uses a nonadaptive selector. In the second phase (classification) we use a feed-forward neural network based on the back-propagation learning method. Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

The architecture of the adaptive metaclassifier M-BP Advanced Computer Architecture & Processing Systems Research

The architecture of the adaptive metaclassifier M-BP Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

Classification accuracy Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research.

Classification accuracy Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

Time necessary for reaching the given total error Advanced Computer Architecture & Processing Systems

Time necessary for reaching the given total error Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

Conclusions n n This new adaptive meta-classifier uses 8 types of SVM classifiers and

Conclusions n n This new adaptive meta-classifier uses 8 types of SVM classifiers and one Naïve Bayes type classifier to achieve the transposition of the input data from a largescale space into a much smaller size space. The best results (99. 74% in terms of classification accuracy) were obtained using a neural network with 192 neurons in the hidden layer. The meta-classifier managed to exceed the maximum "theoretical" limit of 98. 63% which could be reached by an ideal non-adaptive meta-classifier that always chose the correct prediction if at least one classifier provide it. For Reuters 2000 text documents we obtained classification accuracy up to 99. 74%. Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

Some Refererences – Computer Architectures n n n n L. VINTAN, A. GELLERT, A.

Some Refererences – Computer Architectures n n n n L. VINTAN, A. GELLERT, A. FLOREA, M. OANCEA, C. EGAN – Understanding Prediction Limits through Unbiased Branches, Eleventh Asia-Pacific Computer Systems Architecture Conference, Shanghai 6 -8 th, September, 2006 - http: //webspace. ulbsibiu. ro/lucian. vintan/html/LNCS. pdf A. GELLERT, A. FLOREA, M. VINTAN, C. EGAN, L. VINTAN - Unbiased Branches: An Open Problem, The Twelfth Asia-Pacific Computer Systems Architecture Conference (ACSAC 2007), Seoul, Korea, August 23 -25 th, 2007 http: //webspace. ulbsibiu. ro/lucian. vintan/html/acsac 2007. pdf VINTAN L. N. , FLOREA A. , GELLERT A. – Random Degrees of Unbiased Branches, Proceedings of The Romanian Academy, Series A: Mathematics, Physics, Technical Sciences, Information Science, Volume 9, Number 3, pp. 259 - 268, Bucharest, 2008 http: //www. academiaromana. ro/sectii 2002/proceedings/doc 2008 -3/13 -Vintan. pdf A. GELLERT, A. FLOREA, L. VINTAN. - Exploiting Selective Instruction Reuse and Value Prediction in a Superscalar Architecture, Journal of Systems Architecture, vol. 55, issues 3, pp. 188 -195, ISSN 1383 -7621, Elsevier, 2009 http: //webspace. ulbsibiu. ro/lucian. vintan/html/jsa 2009. pdf GELLERT A. , PALERMO G. , ZACCARIA V. , FLOREA A. , VINTAN L. , SILVANO C. - Energy. Performance Design Space Exploration in SMT Architectures Exploiting Selective Load Value Predictions, Design, Automation & Test in Europe International Conference (DATE 2010), March 8 -12, 2010, Dresden, Germany - http: //webspace. ulbsibiu. ro/lucian. vintan/html/Date_2010. pdf CALBOREAN H. , VINTAN L. - An Automatic Design Space Exploration Framework for Multicore Architecture Optimizations, Proceedings of The 9 -th IEEE Ro. Edu. Net International Conference, ISBN , Sibiu, June 24 -26, 2010 - http: //roedu 2010. ulbsibiu. ro/ (indexata IEEE Xplore Digital Library) RADU C. , VINTAN L. - Optimizing Application Mapping Algorithms for No. Cs through a Unified Framework, Proceedings of The 9 -th IEEE Ro. Edu. Net International Conference, ISBN , Sibiu, June 24 -26, 2010 - http: //roedu 2010. ulbsibiu. ro/ (indexata IEEE Xplore Digital Library) L. N. VINTAN - Direcţii de cercetare în domeniul sistemelor multicore / Main Challenges in Multicore Architecture Research, Revista Romana de Informatica si Automatica, ISSN: 12201758, ICI Bucuresti, vol. 19, nr. 3, 2009, v. http: //www. ici. ro/RRIA/ria 2009_3/index. html Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

References (1/2) - CFD Calculation 1. 2. 3. 4. 5. 6. 7. 8. 9.

References (1/2) - CFD Calculation 1. 2. 3. 4. 5. 6. 7. 8. 9. J. Hu and R. Marculescu, “Energy-aware mapping for tile-based No. C architectures under performance constraints, ” in Proceedings of the 2003 Asia and South Pacific Design Automation Conference. Kitakyushu, Japan: ACM, 2003, pp. 233– 239. R. Marculescu and J. Hu, “Energy- and performance-aware mapping for regular No. C architectures, ” IEEE Transactions on Computer. Aided Design of Integrated Circuits and Systems, vol. 24, no. 4, pp. 551– 562, 2005. S. Murali and G. D. Micheli, “Bandwidth-Constrained mapping of cores onto No. C architectures, ” in Proceedings of the conference on Design, Automation and Test in Europe - Volume 2. IEEE Computer Society, 2004, p. 20896. K. Srinivasan and K. S. Chatha, “A technique for low energy mapping and routing in network-on-chip architectures, ” in Proceedings of the 2005 international symposium on Low power electronics and design. San Diego, CA, USA: ACM, 2005, pp. 387– 392. G. Ascia, V. Catania, and M. Palesi, “Multi-objective mapping for mesh-based No. C architectures, ” in Proceedings of the 2 nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis. Stockholm, Sweden: ACM, 2004, pp. 182– 187. J. P. Soininen and T. Salminen, “Evaluating application mapping using network simulation, ” Proc of the Inter Symp on Systemon. Chip, vol. 1100, no. Kaitovyl 1, p. 2730, 2003. (2010) The System. C website. [Online]. Available: http: //www. systemc. org S. Murali and G. D. Micheli, “SUNMAP: a tool for automatic topology selection and generation for No. Cs, ” in Proceedings of the 41 st annual Design Automation Conference. San Diego, CA, USA: ACM, 2004, pp. 914– 919. C. Grecu, A. Ivanov, P. Pande, A. Jantsch, E. Salminen, U. Ogras, and R. Marculescu, “Towards open Network-on-Chip benchmarks, ” in Proceedings of the First International Symposium on Networks-on. Chip. IEEE Computer Society, 2007, p. 205. Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

References (2/2) - CFD Calculation 10. 11. 12. 13. 14. 15. 16. 17. 18.

References (2/2) - CFD Calculation 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. S. Mahadevan, F. Angiolini, M. Storgaard, R. G. Olsen, J. Sparso, and J. Madsen, “A network traffic generator model for fast Network-on-Chip simulation, ” in Proceedings of the conference on Design, Automation and Test in Europe - Volume 2. IEEE Computer Society, 2005, pp. 780– 785. R. P. Dick, D. L. Rhodes, and W. Wolf, “TGFF: task graphs for free, ” in Proceedings of the 6 th international workshop on Hardware/software codesign. Seattle, Washington, United States: IEEE Computer Society, 1998, pp. 97– 101. (2010) The Embedded System Synthesis Benchmarks Suite (E 3 S) website. [Online]. Available: http: //ziyang. eecs. umich. edu/~dickrp/e 3 s/ (2010) The Embedded Microprocessor Benchmark Consortium (EEMBC) website. [Online]. Available: http: //www. eembc. org (2010) The ns-3 network simulator website. [Online]. Available: http: //www. nsnam. org/ H. vom Lehn, K. Wehrle, and E. Weing¨artner, “A performance comparison of recent network simulators, ” 2009 IEEE International Conference on Communications, pp. 1– 5, 2009. S. Schlingmann, “Selbstoptimierendes routing in einem network-on-a-chip, ” Master’s thesis, University of Augsburg, 2007. J. Duato, S. Yalamanchili, and L. M. Ni, Interconnection Networks: An Engineering Approach, 1 st ed. Institute of Electrical & Electronics Enginee, 1997. S. E. Lee and N. Bagherzadeh, “Increasing the throughput of an adaptive router in network-onchip (No. C), ” in Proceedings of the 4 th international conference on Hardware/software codesign and system synthesis. Seoul, Korea: ACM, 2006, pp. 82– 87. E. Salmien, A. Kulmala, and T. D. Hamalainen, “Survey of network-on-chip proposals, ” White paper, © OCP-IP, Tampere University of Technology, March 2008. [On-line]. Available: http: //ocpip. biz/uploads/documents/OCPIP_Survey_of_No. C_Proposals_White_Paper_April_2008. pdf Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php

References - Meta-classifiers for Text Documents 1. 2. 3. CRETULESCU R. , MORARIU D.

References - Meta-classifiers for Text Documents 1. 2. 3. CRETULESCU R. , MORARIU D. , VINTAN L. – Eurovision-like weighted Non-Adaptive Meta-classifier for Text Documents, Proceedings of the 8 th Ro. Edu. Net IEEE International Conference Networking in Education and Research, pp. 145150, ISBN 978 -606 -8085 -15 -9, Galati, December 2009 (indexata ISI Web of Science - http: //apps. isiknowledge. com/) MORARIU D. , CRETULESCU R. , VINTAN L. – Improving a SVM Meta-classifier for Text Documents by using Naïve Bayes, International Journal of Computers, Communications & Control (IJCCC), Agora University Editing House - CCC Publications, ISSN 1841 – 9836, E-ISSN 1841 -9844, Vol. V, No. 3, pp. 351 -361, 2010 CRETULESCU R. , MORARIU D. , VINTAN L. , COMAN I. D. – An Adaptive Meta-classifier for Text Documents, The 16 th International Conference on Information Systems Analysis and Synthesis: ISAS 2010, Orlando Florida, USA, April 6 th – 9 th 2010 Advanced Computer Architecture & Processing Systems Research Lab http: //acaps. ulbsibiu. ro/research. php