OnChip Bus Speaker TianSheuan Chang July 2004 SIP

On-Chip Bus Speaker: Tian-Sheuan Chang July, 2004 S&IP Consortium Course Material

Goal of This Lab v Understand how AHB-Lite works. v Learn how to add new slaves. v Learn to verify AHB-Lite compliance of a slave. S&IP Consortium Course Material 2

Outline v AMBA AHB system v AHB-Lite system v AHB compliance verification v Lab – On-chip bus: AHB-Lite S&IP Consortium Course Material 3

Typical AMBA system S&IP Consortium Course Material 4

An AHB System HBUSREQ_x HGRANT_x HSEL_x S&IP Consortium Course Material 5

Components in AHB (1/2) v Master v. AHB master is able to initiate read and write operations by providing an address and control information. Only one bus master is allowed to actively use the bus at any one time. (max. 16) v Slave v. AHB slave responds to a read or write operation within a given address-space range. The bus slave signals back to the active master the success, failure or waiting of the data transfer. S&IP Consortium Course Material 6

Components in AHB (2/2) v Arbiter v. AHB arbiter ensures that only one bus master at a time is allowed to initiate data transfers. v Decoder v. AHB decoder is used to decode the address of each transfer and provide a select signal for the slave that is involved in the transfer. A single centralized decoder is required in all AHB implementations. S&IP Consortium Course Material 7

AHB Signals v AHB Signals can be classified as v. Clock (HCLK) v. Address and read/write data (HADDR, HRDATA, HWDATA) v. Arbitration (HGRANTx, HMASTER, HMASTLOCK, …) v. Control signal (HRESETn, …) v. Response signal(HREADY, HRESP) S&IP Consortium Course Material 8

AHB Transfer Signals v Transfer signals v. HCLK vbus clock. All signal timings are related to the rising edge. v. HADDR[31: 0] v 32 bits system bus v. HWDATA/HRDATA [31: 0] v 32 bits write/read data bus v. HWRITE v. High: write data v. Low: read data v. HREADY v. Transfer done S&IP Consortium Course Material 9

AHB Basic Transfer v Each transfer consists of v An address and control cycle v One or more cycles for the data S&IP Consortium Course Material 10

AHB Control Signals v Control signals v. HTRANS[1: 0] Ø Current transfer type v. HBURST[2: 0] Ø When sequential transfer, control transfer relation v. HSIZE[2: 0] Ø Control transfer size=2^HSIZE bytes(max=1024 bits) v. HPROT[3: 0] Ø Protection data S&IP Consortium Course Material 11

AHB Control Signal - HTRANS v HTRANS[1: 0] v. IDLE: master don’t need data to be transfered v. BUSY: allows bus masters to insert IDLE cycles in the middle of bursts of transfers. v. NONSEQ: The address and control signals are unrelated to the previous transfer. v. SEQ: the address is related to the previous transfer. S&IP Consortium Course Material 12

AHB Signals - HBURST S&IP Consortium Course Material 13

AHB Signals - HBURST S&IP Consortium Course Material 14

AHB Response Signals v Response signals v. HREADY Ø Transfer done, ready for next transfer v. HRESP[1: 0] Ø OKAY transfer complete Ø ERROR transfer failure(ex: write ROM) Ø RETRY higher priority master can access bus Ø SPLIT other master can access bus S&IP Consortium Course Material 15

AHB Arbitration Signals v Arbitration signals v. HGRANTx Ø Select active bus master v. HMASTER[3: 0] Ø Multiplex signals that sent from master to slave v. HMASTLOCK Ø Locked sequence S&IP Consortium Course Material 16

Master Signals S&IP Consortium Course Material 17

Arbiters Signals S&IP Consortium Course Material 18

Slave Signals S&IP Consortium Course Material 19

Outline v AMBA AHB system v AHB-Lite system v AHB compliance verification v Lab 5 – On-chip bus: AHB-Lite S&IP Consortium Course Material 20

Logic Module Memory Map S&IP Consortium Course Material 21

LM AHB-Lite Block Diagram S&IP Consortium Course Material 22

Integrator LM Block Diagram S&IP Consortium Course Material 23

Notes about LM AHB-Lite system v LM AHB-Lite is a slave in Integrator system v Uses bi-directional tri-state signals v. HDATA v. SDATA v. HREADY v AHB ZBT SRAM controller needs ZBT to be able to read/write without dead cycle. v. HREADY always HIGH No wait-state access v. ZBT Zero Bus Turn-around S&IP Consortium Course Material 24

Modified AHB-Lite system(1/1) v Modified from LM AHB-Lite system v. Replaced bi-directional signal with independent input and output signals Ø HDATA HWDATA/HRDATA Ø SDATA SWDATA/SRDATA Ø HREADYout/HREADY (internal) S&IP Consortium Course Material 25

Modified AHB-Lite system(2/2) v Added 2 more modules v. AHB_HC_master Ø Master module to drive test pattern to AHB-Lite v. SRAM_8 X 8 X 4096 Ø Connected to ZBT SRAM controller Ø Limitation: 16 KB (originally was 1 MB on LM) Cannot perform read after write immediately due to AHB pipeline access characteristic. v Removed some signals (pins) v. Flash related signals v. TDI, TDO, RTCK, etc. S&IP Consortium Course Material 26

AHB-Lite system diagram S&IP Consortium Course Material 27

AHB-lite Access (2/2) v Master checks HREADYin v. HREADYin LO: hold control v. HREADYin HI: initiates access request Ø Read/write Ø Transfer type Ø Transfer size v Decoder decodes access address v. HDRID=0 x. C First LM v. HADDR[27: 20]= 0 x 20 ZBT SRAM controller v. HSEL_zbtssram=1’b 1 send slave select signal S&IP Consortium Course Material 28

AHB-lite Access (1/2) v ZBT SRAM controller v. Write: master send HWDATA to slave in data phase v. Read: slave returns HRDATA to MUX v MUX slave to master read data: v. HSEL_zbtssram=1’b 1 select HRDATA from ZBT SRAM controller to send to master Ø Ready signals Ø Response signals S&IP Consortium Course Material 29

Outline v AMBA AHB system v AHB-Lite system v AHB compliance verification v Lab – On-chip bus: AHB-Lite S&IP Consortium Course Material 30

Compliance check method (1/2) v Simulation check (coverage driven) v. Create check list according to specification v. Create test pattern to hit all the cases in check list Ø Synopsys Design. Ware Verification IP (VIP) + Vera Ø ARM AMBA Compliance Test-bench (ACT) Ø Manually check (most error prone) v. May not cover some corner case Ø 100% coverage (of check list) does not suggest 100% proven S&IP Consortium Course Material 31

Compliance check method (2/2) v Formal techniques v. Property and rules extraction v. Model & property checking and state space exploration v. Averants Solidify Solid. AHB Ø If rules are 100% proven, the interface will not violate the rules S&IP Consortium Course Material 32

Example of check list from Design. Ware VIP v State cases State Name # defined values # hits ----------------cv_nseq_rd 1 26 cv_seq_rd 1 14 cv_busy_rd 1 3 cv_nseq_wr 1 9 cv_seq_wr 1 8 cv_busy_wr 1 2 v Transition cases Transition Name # defined transitions # hits ---------------------cv_nseq 2 nseq 1 22 cv_nseq 2 seq 1 5 cv_nseq 2 idle 1 3 cv_nseq 2 busy 1 3 cv_seq 2 seq 1 13 S&IP Consortium Course Material 33

Outline v AMBA AHB system v AHB-Lite system v AHB compliance verification v Lab -On-chip bus: AHB-Lite S&IP Consortium Course Material 34

Lab : On-chip bus: AHB-Lite v Goal v Guidance v Observer the AHB read/write v Familiarize AHB using AHB-Lite v Identify which module defines v Learn how to add new slave into the memory map AHB-Lite v Practice checking the compliance of v Steps an AHB-Lite slave v Run the example AHB-Lite v Observe signals v Principles v AMBA Protocols v Requirements and Exercises v Add a new slave v Check AHB-Lite compliance of the new slave v Discussion v Disadvantage of using AMBA AHB (Overhead) S&IP Consortium Course Material 35

Files Descriptions v Modify AHB_HC_master. v to modify test pattern v Modify AHB_Testbench. v to modify simulation cycles v Modify AHB_Testbench. f to add new files v My. IP. v is the new slave to be added into AHB-Lite Files Description AMBA_declare. v /beh AMBA related predefined keywords AHB_HC_master. v /beh AHB_HC_master behavioral module SRAM_8 X 4 X 4096. v /beh 16 KB SRAM module RA 1 SH. v /beh SRAM behavioral model AHB_Testbench. v /beh AHB_Testbench top module including AHB_HC_master, SRAM_8 X 4 X 4096, and RA 1 SH AHBAHBTop. v /rtl AHBAHBTop modified module AHBDecoder. v /rtl AHBDecoder module AHBMux. S 2 M. v /rtl AHBMux. S 2 M module AHBZBTRAM. v /rtl AHBZBTRAM module AHB 2 APB. v /rtl AHB 2 APB module, it is also a slave AHBAPBSys. v /rtl AHBAPBSys module APBRegs. v /rtl APBRegs module APBIntcon. v /rtl APBIntcon module My. IP. v /rtl Slave to be added into AHB-Lite AHB_Testbench. f /verif File lists of the whole test bench /verif File lists of AHBAHBTop and its submodules LM_AHBAPB. f S&IP Consortium Course Material Path 36

Accesses made by AHB_HC_master v 7 Accesses v Data and control are not within the same cycle No. HWRITE HSIZE HADDR HRDATA/ HWDATA 1 Read 32 -bit 0 xc 2000000 0 x. XXXX 2 Read 32 -bit 0 xc 2000010 0 x. XXXX 3 Write 32 -bit 0 xc 2000000 0 x 00001234 4 Read 32 -bit 0 xc 2000010 0 x 00001234 5 Read 32 -bit 0 xc 2000010 0 x. XXXX 6 Read 32 -bit 0 xc 2000000 0 x 00001234 7 Read 32 -bit 0 xc 2000010 0 x. XXXX S&IP Consortium Course Material Remarks SRAM cannot read immediately after write using ZBT SRAM controller. 37

Lab Requirements for Students v Run the modified AHB-Lite system using verilog simulator v. Use Debussy n. Wave to observe the AHB signals during the 7 accesses intiated by AHB_HC_master. v. Explain the waveforms to TA, they must point out the pipeline transfer characteristic of AHB bus. S&IP Consortium Course Material 38

Lab Exercise for Students v Add a new slave device: My. IP to the modified AHBLite system. v. My. IP is a slave device provided for exercise v Verify the slave’s AHB compliance v. Make check lists Ø Nonseq_16_write, write_after_read_16, etc. v. Write test pattern to check the check list for compliance S&IP Consortium Course Material 39

References [1] AMBA Specification, Rev. May, 2. 0, 1999. [2] High-Speed Single-Port SRAM (HS-SRAM-SP) Generator User Manual, Artisan Components Inc. , Release 4. 0, Aug. 2000. [3] Debussy User Guide and Tutorial, NOVAS Software Inc. , Sept. 2002. [4] Compatibility of Network SRAM and ZBT SRAM, Mitsubishi LSIs Application Note (AP-S 001 E), Rev. C, Renesas Tech. Corp. , Sept. 2002. [5] Design. Ware AHB Verification IP Databook, ver. 2. 0 a, Synopsys Inc. , July 2002. [6] VMT User Manual, Release 2. 0 a, Synopsys Inc. , July 2002. [7] Vera User Guide, ver. 5. 1, Synopsys Inc. , June 2002. [8] Solid. AMBA, Averant Inc. , Dec. 2003. S&IP Consortium Course Material 40