Old IDESA and New IDESA2 European Training Programs

Old IDESA and New IDESA-2 European Training Programs for Implementation of DSM CMOS ASICs Wieslaw Kuzmicz, Warsaw University of Technology, Warsaw, Poland, wbk@imio. pw. edu. pl Bart De. Mey, Microelectronics Training Center, imec, Leuven, Belgium, Bart. De. Mey@imec. be with all project partners

IDESA and IDESA-2 are FP 7 projects funded by the European Union.

IDESA - IC Design Skills for Advanced DSM Technologies Outline Motivation and goals More Moore, less designs More Moore, more money More Moore, more problems Small but not beautiful IDESA: 2008 - 2010 About the project Four hands-on courses Advanced seminars Outcomes, problems and lessons learned IDESA-2: 2010 - 2012 What’s old, what’s new Practical aspects Information Conclusions EWME 2010, Darmstadt, May 11, 2010

IDESA - IC Design Skills for Advanced DSM Technologies 2008: more Moore, less designs Facts: Number of university designs submitted to EUROPRACTICE MPW service started to decrease in 1997: ~ 400 2003: ~ 200 Many universities abandoned silicon implementation oriented courses Digital system design: software and FPGA only Analog design: slowly disappearing, together with device physics and design Consequence: Europe has almost lost ASIC production to Far East… Is Europe going to lose design as well? EWME 2010, Darmstadt, May 11, 2010

IDESA - IC Design Skills for Advanced DSM Technologies 2008: more Moore, more money? Cost of processed silicon goes up… …but the number of devices per unit area goes up faster. -> the cost of a single transistor goes down, -> larger, more complex and less expensive So. Cs. This is the driving force for the industry. But what helps big IDMs focusing on large volume manufacturing, kills silicon implementation activities at universities! University designs do not have millions of transistors… …but the minimum silicon area must be paid for. -> the cost of a single transistor goes up, -> silicon prototyping becomes prohibitively expensive. EWME 2010, Darmstadt, May 11, 2010 5

IDESA - IC Design Skills for Advanced DSM Technologies 2008: more Moore, less designs Is the silicon cost the only reason? Introduction of mini@sic - reduced cost MPW option Extra EU financial support for university DSM designs Source: EUROPRACTICE EWME 2010, Darmstadt, May 11, 2010 6

IDESA - IC Design Skills for Advanced DSM Technologies 2008: more Moore, more problems Density rules and dummy fills No. of design rules 700 600 500 400 300 Resolution enhancement techniques 200 100 350 250 180 150 120 90 nm Technology node Sources: Medea+; TSMC; IDESA course OPC picture courtesy of J-M. Brunet, IEEE Web Seminar, November 9, 2006, reproduced with permission EWME 2010, Darmstadt, May 11, 2010 7

IDESA - IC Design Skills for Advanced DSM Technologies 2008: small but not beautiful • DSM devices: – – – • Complex structures: STI, triple well, retrograde doping, LDD and pocket implants, multilayer gate stack Complex physics: SCE and RSCE, DIBL, poly depletion, gate tunneling current, band to band junction leakage, stress effects, ballistic transport, quantum effects Complex models Large variability Low VDD and VGS voltages Low threshold voltage, high subthreshold “off” current DSM circuit and system design more complicated – – Digital design: “low leakage” architectures, high power density, complex timing verification, … Analog design: low supply voltage, large mismatch, high device output conductance, … EWME 2010, Darmstadt, May 11, 2010 8

IDESA - IC Design Skills for Advanced DSM Technologies IDESA: about the project Mission: To bridge the gap between the industrial DSM design flows, methodologies and tools, and the design knowledge, competences and skills at European universities. Main actions: Four advanced hands-on courses focusing on 90 nm technology: Advanced analog implementation flow Advanced RF implementation flow Advanced digital physical implementation flow Design for manufacturing Advanced seminars (1 to 3 hours each) introducing problems beyond 90 nm IDESA Workshop EWME 2010, Darmstadt, May 11, 2010 9

IDESA - IC Design Skills for Advanced DSM Technologies IDESA: four advanced hands-on courses Course brochures available on IDESA Web site EWME 2010, Darmstadt, May 11, 2010 10

IDESA - IC Design Skills for Advanced DSM Technologies IDESA: advanced courses - locations Country No. of locations No. of courses Belgium 2 8 Czech Rep. 1 1 France 1 1 Greece 1 2 Italy 2 2 Poland 3 3 Slovakia 1 2 Spain 1 1 Sweden 1 1 Switzerland 1 1 The Netherlands 1 1 UK 2 4 Total 17 27 Hosts: universities and public research institutes Good geographical coverage One course cancelled due to insufficient number of registered participants EWME 2010, Darmstadt, May 11, 2010 11

IDESA - IC Design Skills for Advanced DSM Technologies IDESA: advanced courses - attendees Total number: 429 from 132 institutions and 26 countries 20 EU member states Highest numbers (30+) from Belgium, Spain, UK, Italy, Germany and Poland Seven EU countries, among them Baltic states, not represented Non-EU: Belarus, Norway, Russia, Serbia, Switzerland, Turkey EWME 2010, Darmstadt, May 11, 2010 12

IDESA - IC Design Skills for Advanced DSM Technologies IDESA: advanced seminars Recorded and distributed in electronic form (streaming and files for download), 22 available (more expected) Prepared mainly by external invited experts from universities, research institutes, EDA companies, IDMs Free reuse allowed for teaching EWME 2010, Darmstadt, May 11, 2010 13

IDESA - IC Design Skills for Advanced DSM Technologies IDESA: outcomes Very high overall satisfaction level Most course attendees declared that the courses were very relevant to their research and/or teaching , esp. lab hands-on sessions Most course attendees declared that they were going to design DSM chips in the next year or two Start of IDESA Introduction of mini@sic Source: EUROPRACTICE Extra EU financial support EWME 2010, Darmstadt, May 11, 2010 14

IDESA - IC Design Skills for Advanced DSM Technologies IDESA: problems and lessons learned Joint course development: easier than expected Logistics: Web based registration (handled by RAL) Temporary software licenses (handled by RAL and software vendors) Remote access to computer networks at course host institutions for trainers (handled by all course hosts) Real design kits (90 nm from TSMC), individual NDA required for all course attendees (handled by IMEC) Marketing: Web site, e-mail campaigns, conference presentations - still not 100% successful All analog, digital and RF-oriented courses almost fully booked (average: 16 to 18 attendees per course); Df. M course less popular Many non-EU participants had to cancel their course bookings due to financial crisis, despite travel grants offered IDESA: a success, but about 20% of EU academic staff and Ph. D students reached only! EWME 2010, Darmstadt, May 11, 2010 15

IDESA - IC Design Skills for Advanced DSM Technologies IDESA-2: main actions • Four advanced hands-on courses - updated: – – • • • Advanced analog implementation flow Advanced RF implementation flow Advanced digital physical implementation flow (2 versions: CADENCE - based and SYNOPSYS - based) Design for manufacturing Courses will be repeated again at various locations 7 times each Universities and institutes: proposals for course hosting are welcome! NEW: courses will be open to SMEs Advanced seminars (1 to 3 hours each) introducing problems beyond 90 nm, 65 nm, 45 nm - more will be added Proposals for new seminars are welcome! EWME 2010, Darmstadt, May 11, 2010 16

IDESA - IC Design Skills for Advanced DSM Technologies Advanced analog implementation flow Technology aspects in 90 nm analog - lecture Modeling issues - lecture Hands-on evaluation versus simulation accuracy - lecture and lab Transistor level and behavioural level design - lecture and lab Analog cell trimming using digital functions - lecture Mixed mode design and its simulation methodology - lab Mismatch and yield modeling and analysis - lecture Analog modeling and circuit optimization - lecture Analog circuit optimization and layout - lab 5 days Instructors from IMEC, EPFL, KUL EWME 2010, Darmstadt, May 11, 2010 17

IDESA - IC Design Skills for Advanced DSM Technologies Advanced RF implementation flow • • • Technology aspects in 90 nm mixed signal and RF - lecture Mosfet modeling - lecture Microwave passive component design and simulation - lecture and lab Testing and microwave measurements - lecture and lab Mismatch modeling and simulation - lecture and lab Mixed mode So. C design and its simulation methodology - lecture Analog and RF cell trimming using digital functions - lecture and lab 90 nm design verification - lecture and lab Circuit packaging - lecture and lab Electrostatic discharge protection - lecture and lab 5 days Instructors: from IMEC, EPFL, TU Delft, WUT EWME 2010, Darmstadt, May 11, 2010 18

IDESA - IC Design Skills for Advanced DSM Technologies Advanced digital physical implementation flow Intro: what are the new challenges to design 90 nm So. Cs - lecture Design environment and tool chain - lecture Design synthesis (open SPARC) - lecture and lab Leakage aware design/prevention - lecture Design planning and floorplanning - lecture and lab Library analysis and management - lecture IP integration and management - lecture Low power flow, positioning the different techniques to minimize dynamic and leakage power - lecture and lab Physical synthesis - placement and optimization - lecture and lab Multiple clock tree synthesis - lecture Physical synthesis - design for test - lecture Physical synthesis - multimode and multicorner - lecture (Continued on the next slide) EWME 2010, Darmstadt, May 11, 2010 19

IDESA - IC Design Skills for Advanced DSM Technologies Advanced digital physical implementation flow (continued) Physical synthesis - routing to GDS 2 - lecture and lab IR drop analysis, requirement to do dynamic power analysis in 90 nm - lecture Multimode, multicorner analysis, on chip variations and statistical static timing analysis, signoff analysis icnluding signal integrity lecture and lab Sign-off - lecture Design finishing and layout verification - lecture and lab Tape-out - lecture 5 days Instructors: from RAL STFC, IMEC, WUT EWME 2010, Darmstadt, May 11, 2010 20

IDESA - IC Design Skills for Advanced DSM Technologies Design for Manufacturing flow Introduction to manufacturing and yield. Process flow - lecture Defectivity - lecture Post-layout and manufacturability - lecture Litho simulation and process window - lab Design and layout for litho manufacturability - lecture Examples for other initiatives for post-layout manufacturability lecture Backend metallization: dual Damascene process, copper fill lecture DFM solutions - demo lab Yield analysis - demo lab Design for test and yield management - lecture 4 days Instructors: from IMEC EWME 2010, Darmstadt, May 11, 2010 21

IDESA - IC Design Skills for Advanced DSM Technologies Conditions of participation Courses intended for academic staff (Ph. D students and up), all European universities and public research institutes eligible (priority for EU institutions) Inexpensive (50 € per day); travel and local expenses paid by participants Will be repeated in many places in Europe to reduce travel costs Prerequisites: basic knowledge of VLSI design; some knowledge of Unix will be beneficial 18 - 24 persons per course (limited by number of computer seats in host institution) Materials can be freely reused in training IC designers from SMEs may participate at cost closer to market prices EWME 2010, Darmstadt, May 11, 2010 22

IDESA - IC Design Skills for Advanced DSM Technologies Calendar 2010: First courses already scheduled Df. M: IMEC (Belgium), 26 - 29 October 2010 Analog: RAL (UK), 6 - 10 September 2010 Project Web site will announce next courses Further dates and host sites to be determined Any European university and public research institutie can host a course Main requirements: availability of technical infrastructure and sufficiently high expected number of participants Course fees go to the host institution, to cover local costs EWME 2010, Darmstadt, May 11, 2010 23

IDESA - IC Design Skills for Advanced DSM Technologies Information IDESA Web site: http: //www. idesa-training. org Project coordinator: Dr Bart De. Mey, IMEC, Bart. De. Mey@imec. be IDESA and IDESA-2 project consortium: IMEC, Leuven, Belgium - the coordinator Ecole Polytechnique Fédérale de Lausanne, Switzerland Technische Universiteit Delft, the Netherlands Rutherford Appleton Lab. , STFC, Chilton, UK Slovak University of Technology, Bratislava, Slovakia Warsaw University of Technology, Warsaw, Poland Katholieke Universiteit Leuven, Belgium CEA LETI, Grenoble, France Courses will also be advertised by EUROTRAINING EWME 2010, Darmstadt, May 11, 2010 24

IDESA - IC Design Skills for Advanced DSM Technologies Acknowledgments Collaboration of all the project partners is gratefully acknowledged EWME 2010, Darmstadt, May 11, 2010 25

IDESA 2: Everybody is invited! IC Design Skills for Advanced DSM Technologies