Nyquist Rate ADCs Dr Hossein Shamsi ECE Dept

Nyquist Rate ADCs Dr. Hossein Shamsi ECE Dept, K. N. Toosi University of Technology 0 /30

Content v v v v v Sample & Hold Circuits Voltage Comparators Dual-Slope ADC Flash ADC SAR ADC Cyclic ADC Two-Step ADC Pipelined ADC Time Interleaved ADC 1 /30

Ideal Voltage Comparator 2 /30

Preview - Flash ADC 3 /30

Design Considerations 4 /30

Gain Requirements 5 /30

How to Implement High Gain? 6 /30

How about Using an Op. Amp or OTA? 7 /30

Cascade of Open-Loop Amplifiers 8 /30

Step Response (1) 9 /30

Step Response (2) 10 /30

Delay versus Number of Stages 11 /30

Optimum Number of Stages 12 /30

Optimum Gain per Stage 13 /30

Cascade of "Integrators" (1) 14 /30

Cascade of "Integrators" (2) 15 /30

Latched Comparator (2) 16 /30

Comparison 17 /30

Latch "Gain” 18 /30

Metastability (1) 20 /30

Metastability (2) 21 /30

Metastability (3) 22 /30

CMOS comparators 23 /30

Input Referred Offset 24 /30

Amplifier Offset Cancellation (1) 25 /30

Amplifier Offset Cancellation (2) 26 /30

Output Series Cancellation 27 /30

Input Series Cancellation 28 /30

Overdrive Recovery 29 /30

Comparator Example 30 /30