NVM Structures For FPGA Architectures Ali Ahari October

NVM Structures For FPGA Architectures Ali Ahari October 2011 Data Storage Systems and Networks Lab.

Outline • Introduction • New Non-Volatile Memory Structures for FPGA Architectures • 3 D-Non. FAR • RTA 3 P • Conclusion

Introduction • We are going to review 3 papers in this session • Our goal is to make a review on previous works in Reconfigurable Architectures that use NVM in their structure

New Non-Volatile Memory Structures for FPGA Architectures 1 • Classifying FPGAs by the Memory used ▫ SRAM ▫ Flash ▫ Antifuse 1 -TVLSI 2008

SRAM vs. Flash vs. Antifuse Cell Size Speed Configuration SRAM Antifuse Flash Antifuse SRAM Flash Antifuse Flash SRAM Once in whole life Stays even after power off At power up, from external source to chip

Challenges for Flash-based FPGAs • • • High programming voltage and current 10 V vs. 3 V 200 -500µA vs. 1µA Higher mask count Lower performance

Benefits • • Lower Cell size Great speed up at Power-up Saves the data even after power-down Introduces new power saving techniques

Programmable Elements(PEs) FPGA Logical element with threeinput LUT, ﬂip-ﬂop (DFF), and twoinput multiplexer. Example of two logical elements connected together using a switch that is controlled by PE.

Switch with SRAM as its PE

Flash-based switch

Can we combine SRAM with Flash? • Yes! • By using polysilicon-oxide-nitride-oxide-silicon (SONOS) technology • So now we have both ▫ speed of SRAM ▫ ability to store data in the absence of power ▫ Lower cell size

Proposed non-volatile PE for routing switches

PE for conﬁguration of logical elements

Three-input LUT with integrated nonvolatile memory PEs

Non-volatile ﬂip-ﬂop

Conclusion • New structure shows 22% to 36% area savings • Enables new power-down strategies

3 D-Non. FAR 1 • Main ideas: ▫ Using 3 D integration Tech. �High performance �Reduced interconnect resources �High logical density ▫ Using PCM �High performance �Excellent scalability �High density 1 -ISLPED '10 Proceedings of the 16 th ACM/IEEE international symposium on Low power electronics and design

PCM a universal memory replacement

3 D ICs • Advantages: ▫ ▫ ▫ Higher packing density and smaller footprint Shorter global interconnect Flexibility of vertical routing Higher performance Low power Support of heterogenous integration • Drawbacks: ▫ New thermal and power problems

Classical SRAM-based FPGA

Renovated FPGA basic structures with PCM MLC cells

Benefit and Cost • Cost ▫ 10 x-40 x write latency • Benefit ▫ 10 x logical density

3 D Architecture • All non-volatile memory elements are aggregated in one single layer to reduce manufacture cost

3 D Non. FAR vs. Other 3 D Architectures • 3 D-Non. FAR is more favorable in larger devices

Performance and Power evaluation • This evaluation is done by CACTI and PCRAMsim

Total wire-length

Critical Path Delay

Power Consumption • P = Pdyn + Pstatic Power Improvement Plogic, dyn Pmem, dyn Pnet, dyn Pclk, dyn Pstatic

Power Consumption

Paper Conclusion • In average: ▫ ▫ 54. 9% improvement in total wire length 44. 9% improvement in critical path delay 60% area reduction 35. 1% power reduction

New Reprogrammable and Non-Volatile Radiation Tolerant FPGA: RTA 3 P 1 • It is a bunch of physical fault injection tests on A 3 P FPGA-family • There is nothing about architecture and … • Showed some SEE sensitivity 1 - AERO 2008 IEEE

Conclusion • 1 st paper ▫ Lack of measurement methods ▫ Some issues about performance of using NVM FFs • 2 nd paper ▫ A good heterogeneous architecture ▫ No point about manufacturing problems ▫ Good details about measurements • 3 rd paper ▫ Not related to the topic