Numbers Everyone Should Know Jeff Dean Google L

Numbers Everyone Should Know (Jeff Dean, Google) • • • L 1 cache reference: Branch mis-predict: L 2 cache reference: Mutex lock/unlock: Main memory reference Compress 1 K Bytes with Zippy Send 2 K Bytes over 1 GBPS network Read 1 MB sequentially from memory Round trip within data center Disk seek Read 1 MB sequentially from disk Send one packet from CA to Europe 0. 5 ns 7 ns 25 ns 100 ns 3000 ns 20000 ns 250000 ns 500000 ns 1000000 ns 2000000 ns 15000000 ns 2

3 Replacement Algorithms in Data Storage Management • A replacement algorithm decides – Which data entry to be evicted when the data storage is full. – Objective: keep to-be-reused data, replace ones not to-be-reused – Making a critical decision: a miss means an increasingly long delay • Widely used in all memory-capable digital systems – Small buffers: cell phone, Web browsers, e-mail boxes … – Large buffers: virtual memory, I/O buffer, databases … • A simple concept, but hard to optimize – More than 40 years tireless algorithmic and system efforts – LRU-like algorithms/implementations have serious limitations.

4 Least Recent Used (LRU) Replacement • LRU is most commonly used replacement for data management. • Blocks are ordered by an LRU order (from bottom to top) • Blocks enter from the top (MRU), and leave from bottom. (LRU) Move block 2 to The stack is long, the bottom is the only exit. the top of stack 5 • Recency – the distance from a block to the top of the LRU stack 3 2 of Blockto 2 the is itstop distance • Upon a hit –Recency move block to the top of stack Recency = 2 Upon a Hit to 9 1 block 2 LRU stack

5 Least Recent Used (LRU) Replacement • LRU is most commonly used replacement for data management. • Blocks are ordered by an LRU order (from bottom to top) • Blocks enter from the top, and leave Load block 6 from disk from bottom. The stack is long, the bottom is the only exit. Upon a Miss to block 6 • Recency – the distance from a block to the top of the LRU stack 6 Disk 2 3 Put block 6 on 5 the stack top • Upon a hit – move block to the top Replacement – the block 1 at the • Upon a miss –stack evictbottom blockisatevicted the bottom 9 1 LRU stack

LRU is a Classical Problem in Theory and Systems • First LRU paper – L. Belady, IBM System Journal, 1966 • Analysis of LRU algorithms – Aho, Denning & Ulman, JACM, 1971 – Rivest, CACM, 1976 – Sleator & Tarjan, CACM, 1985 – Knuth, J. Algorithm, 1985 – Karp, et. al, J. Algorithms, 1991 • Many papers in systems and databases – ASPLOS, ISCA, SIGMETRICS, SIGMOD, VLDB, USENIX… 6

7 The Problem of LRU: Inability to Deal with Certain Access Patterns • File Scanning – One-time accessed data evict to-be-reused data (cache pollution) – A common data access pattern (50% data in NCAR accessed once) – LRU stack holds them until they reach to the bottom. • Loop-like accesses – A loop size k+1 will miss k times for a LRU stack of k • Access with different frequencies (mixed workloads) – Frequently accessed data can be replaced by infrequent ones

8 Why Flawed LRU is so Powerful in Practice • What is the major flaw? – The assumption of “recent used will be reused” is wrong – This prediction is based on a simple metrics of “recency” – Some are cached too long, some are evicted too early. • Why it is so widely used? – Works well for data accesses following LRU assumption – A simple data structure to implement

Challenges of Addressing the LRU Problem • Two types of Efforts have been made – Detect specific access patterns: handle it case by case – Learn insights into accesses with complex algorithms – Most published papers could not be turned into reality • Two Critical Goals – Fundamentally address the LRU problem – Retain LRU merits: low overhead and its assumption • The goals are achieved by a set of three papers – The LIRS algorithm (SIGMETRICS’ 02) – Clock-pro: a system implementation (USENIX’ 05) – BP-Wrapper: lock-contention free assurance (ICDE’ 09) 9

Outline • The LIRS Algorithm – How the LRU problem is fundamentally addressed – How a data structure with low complexity is built • Clock-pro – Turn LIRS algorithm into system reality • BP-Wrapper – free lock contention so that LIRS and others can be implemented without approximation • What would we do for multicore processors? • Research impact in daily computing operations 10

Recency vs Reuse Distance • Recency – the distance between last reference to the current time • Reuse Distance (Inter reference recency) – the distance between two consecutive reference to the block (deeper and more useful information) . . . 3 4 4 5 3 45 3 Recency = 1 Recency = 2 2 Recency is the distance from a block to the top of the LRU stack 9 8 1 LRU stack 11

12 Recency vs Reuse Distance • Recency – the distance between last reference to the current time • Reuse Distance (Inter reference recency) – the distance between two consecutive reference to the block (deeper and more useful info) IRR = 2 . . . 3 Inter-Reference Recency (IRR) The number of other unique blocks accessed between two consecutive references to the block. 3 4 5 3 4 Recency = 0 5 Recency = 2 5 3 3 2 LRU Stack for HIRs 9 LRU stack 8 IRR is the recency of the block being accessed last time – need an extra stack to help, increasing complexity.

13 Diverse Locality Patterns on an Access Map one-time accesses Logical Block Number loops Virtual Time (Reference Stream) strong locality

14 What Blocks does LRU Cache (measured by IRR)? IRR (Re-use Distance in Blocks) Locality Strength MULTI 2 LRU holds frequently accessed blocks with “absolutely” strong locality. holds one-time accessed blocks (0 locality) Likely to replace other relatively strong locality blocks Cache Size Virtual Time (Reference Stream)

15 LIRS: Only Cache Blocks with Low Reuse Distances IRR (Re-use Distance in Blocks) MULTI 2 Locality Strength Holds strong locality blocks (ranked by reuse distance) Cache Size Virtual Time (Reference Stream)

Basic Ideas of LIRS (SIGMETRICS’ 02) 16 • LIRS: Low Inter-Reference recency Set – Low IRR blocks are kept in buffer cache – High IRR blocks are candidates for replacements • Two stacks are maintained – A large LRU stack contains low IRR resident blocks – A small LRU stack contains high IRR blocks – The large stack also records resident/nonresident high IRR blocks • IRRs are measured by the two stacks – After a hit to a resident high IRR block in small stack, the block becomes low IRR block and goes to the large stack if it can also be found in the large stack => low IRR , otherwise, top it locally – The low IRR block in the bottom stack will become a high IRR block and go to the small stack when the large stack is full.

17 Low Complexity of LIRS • Both recencies and IRRs are recorded in each stack – The block in the bottom of LIRS has the maximum recency – A block is low IRR if it can be found in in both stacks – No explicit comparisons and measurements are needed • Complexity of LIRS = LRU = O(1) although – Additional object movements between two stacks – Pruning operations in stacks

18 Data Structure: Keep LIR Blocks in Cache Low IRR (LIR) blocks and High IRR (HIR) blocks Block Sets LIR block set (size is Llirs ) Physical Cache Llirs Lhirs HIR block set Cache size L = Llirs + Lhirs

19 LIRS Operations • Initialization: All the referenced blocks are given an LIR status until LIR block set is full. We place resident HIR blocks in a small LRU Stack. 5 resident in cache 3 LIR block HIR block 2 6 Cache size L=5 Llir = 3 9 Lhir =2 1 • Upon accessing an LIR block (a hit) • Upon accessing a resident HIR block (a hit) • Upon accessing a non-resident HIR block (a miss) 4 5 8 3 LIRS stack LRU Stack for HIRs

20 Access an LIR Block (a Hit) . . . 5 9 7 5 3 8 4 resident in cache 5 LIR block 3 HIR block Cache size 2 L=5 Llir = 3 1 Lhir =2 6 9 4 5 8 3

21 Access an LIR Block (a Hit) . . . 5 9 7 5 3 8 resident in cache 4 LIR block 5 HIR block Cache size 3 L=5 Llir = 3 2 Lhir =2 1 6 9 5 8 3

22 Access an LIR block (a Hit) . . . 5 9 7 5 3 8 resident in cache 8 LIR block 4 HIR block Cache size 5 L=5 Llir = 3 3 Lhir =2 2 1 6 5 9 3

23 Access a Resident HIR Block (a Hit) . . . 5 9 7 5 3 resident in cache LIR block 3 HIR block Cache size 8 L=5 Llir = 3 4 Lhir =2 5 3 2 5 1 3

24 Access a Resident HIR Block (a Hit) . . . 5 9 7 5 3 resident in cache LIR block 3 HIR block Cache size 8 L=5 Llir = 3 4 Lhir =2 5 2 1 5

25 Access a Resident HIR Block (a Hit) . . . 5 9 7 5 3 resident in cache LIR block HIR block Cache size 3 L=5 Llir = 3 8 Lhir =2 4 5 2 1 1 5

26 Access a Resident HIR Block (a Hit) . . . 5 9 7 5 resident in cache LIR block HIR block Cache size L=5 Llir = 3 Lhir =2 3 8 15 4 5

Access a Non-Resident HIR block (a Miss) . . . 5 9 7 resident in cache LIR block HIR block Cache size L=5 Llir = 3 7 Lhir =2 5 3 8 75 4 1 27

Access a Non-Resident HIR block (a Miss) . . . 5 9 resident in cache LIR block HIR block Cache size 9 L=5 Llir = 3 7 Lhir =2 5 3 8 97 4 5 28

Access a Non-Resident HIR block (a Miss) . . . 5 resident in cache LIR block HIR block 5 Cache size 9 L=5 Llir = 3 7 Lhir =2 5 3 8 9 4 7 29

Access a Non-Resident HIR block (a Miss) . . . resident in cache LIR block HIR block 5 Cache size 9 L=5 Llir = 3 7 Lhir =2 3 8 4 9 30

31 A Simplified Finite Automata for LRU Upon a block access Hit (placement it on the top) Miss (fetch data and place on the top) Operations on LRU stack block evicts (remove the block in the bottom)

32 A Simplified Finite Automata for LIRS Upon a block access ack HIR st o t n o i Demot Block evicts Operations on HIR stack Miss (with a record) Hit Operations on LIR stack Hit/promotion to LIR stack Operations on HIR stack Miss/promotion to LIR stack Pruning Add ar eco rd Hit Miss (no record) on res ide nt Operations on HIR stack Miss HIR Block evicts

A Simplified Finite Automata for LIRS Upon a block access ack HIR st o t n o i Demot Operations on HIR stack Miss (with a record) Hit Operations on LIR stack Hit/promotion to LIR stack Operations on HIR stack Miss/promotion to LIR stack Pruning Add ar eco rd Hit Miss (no record) on res ide nt Operations on HIR stack Miss HIR Block evicts

34 How LIRS addresses the LRU problem § § § File scanning: one-time access blocks will be replaced timely; (due to their high IRRs) Loop-like accesses: a section of loop data will be protected in low IRR stack; (misses only happen in the high IRR stack) Accesses with distinct frequencies: Frequently accessed blocks in short reuse distance will NOT be replaced. (dynamic status changes)

35 Performance Evaluation l Trace-driven simulation on different patterns shows – LIRS outperforms existing replacement algorithms in almost all the cases. – The performance of LIRS is not sensitive to its only parameter Lhirs. – Performance is not affected even when LIRS stack size is bounded. – The time/space overhead is as low as LRU. – LRU is a special case of LIRS (without recording resident and non-resident HIR blocks, in the large stack).

39 Two Technical Issues to Turn it into Reality l High overhead in implementations l l High lock contention cost l l l For each data access, a set of operations defined in replacement algorithms (e. g. LRU or LIRS) are performed This is not affordable to any systems, e. g. OS, buffer caches … An approximation with reduced operations is required in practice For concurrent accesses, the stack(s) need to be locked for each operation Lock contention limits the scalability of the system Clock-pro and BP-Wrapper addressed these two issues

40 Only Approximations can be Implemented in OS l l The dynamic changes in LRU and LIRS cause some computing overhead, thus OS kernels cannot directly adopt them. An approximation reduce overhead at the cost of lower accuracy. The clock algorithm for LRU approximation was first implemented in the Multics system in 1968 at MIT by Corbato (1990 Turing Award Laureate) Objective: LIRS approximation for OS kernels.

41 Basic Operations of CLOCK Replacement § All the resident pages are placed around a circular list, like a clock; § Each page is associated with a reference bit, indicating if the page has been accessed. 0 0 1 0 On a block HIT 1 CLOCK hand 0 Upon a HIT: Set reference bit to 1 No algorithm operations 0 1 0 0 0 1 1 0

43 Unbalanced R&D on LRU versus CLOCK LRU related work q FBR (1990, SIGMETRICS) CLOCK related work q GCLOCK (1978, ACM TDBS) q LRU-2 (1993, SIGMOD) q 2 Q (1994, VLDB) q SEQ (1997, SIGMETRICS) q LRFU (1999, OSDI) q EELRU (1999, SIGMETRICS) q MQ (2001, USENIX) q LIRS (2002, SIGMETRICS) q ARC (2003, FAST) 1968, Corbato 2003, Corbato q CAR (2004, FAST) q CLOCK-Pro (2005, USENIX)

0 1 Cold resident 0 1 45 CLOCK-Pro (USENIX’ 05) Hot 1 Hand-hot: find 2 a hot page 3 to be demoted 0 0 into a cold page. 0 4 Cold non-resident 0 5 24 0 23 0 1 22 0 hand-hot 0 6 0 20 1 19 hand-cold Hand-cold is used to find a page for 7 replacement. 8 hand-test All hands move in the clockwise direction. 0 9 Hand-test: (1) to determine if a cold 0 page is promoted to be hot; (2) 10 15 0 out 1 pages remove non-resident cold Two reasons for a resident cold page: 14 of the clock. 11 (1) A fresh replacement: a first access. 12 13 (2) It is demoted from a hot page. 21 0 18 0 17 16

50 History of Buffer Pool's Caching Management in Postgre. SQL • 1996 -2000: LRU (suffer lock contention moderately due to low concurrency) • 2000 -2003: LRU-k (hit ratio outperforms LRU, but lock contention became more serious) • 2004: ARC/CAR are implemented, but quickly removed due to an IBM patent protection. • 2005: 2 Q was implemented (hit ratios were further improved, but lock contention was high) • 2006 to now: CLOCK (approximation of LRU, lock contention is reduced, but hit ratio is the lowest compared with all the previous ones)

Trade-offs between Hit Ratios and Low Lock Contention for high hit ratio LRU-k, 2 Q, LIRS, ARC, SEQ, …. …… …… ? 51 for high scalability Our Goal: to have both! CLOCK, CLOCK-Pro, and CAR Lock Low Lock Synchronization modify data structures Update page metadata Ø Clock-based approximations lower hit ratios (compared to original ones). Ø The transformation can be difficult and demand great efforts; Ø Some algorithms do not have clock-based approximations. Ø 51

Reducing Lock Contention by Batching Requests Replacement Algorithm (modify data structures, etc. ) Buffer Pool Page hit One batch queue per thread Fulfill page request Fetch the page directly. Commit assess history for a set of replacement operations Replacement Algorithm (modify data structures, etc. ) Buffer Pool Ø 52 52

53 Reducing Lock Holding Time by Prefetching Thread 2 Data Cache Miss Stall Thread 1 Time Thread 2 Pre-read data that will be accessed in the critical section Thread 1 Time Ø 53

54 Lock Contention Reduction by BP-Wrapper (ICDE’ 09) Lock contention: a lock cannot be obtained without blocking; Number of lock acquisitions (contention) per million page accesses. Reduced by over 7000 times! Ø 54

55 Impact of LIRS in Academic Community l LIRS is a benchmark to compare replacement algorithms – Reuse distance is first used in replacement algorithm design – A paper in SIGMETRICS’ 05 confirmed that LIRS outperforms all the other replacement. – LIRS has become a topic to teach in both graduate and undergraduate classes of OS, performance evaluation, and databases at many US universities. – The LIRS paper (SIGMETRICS’ 02) is highly and continuously cited. l Linux Memory Management group has established an Internet Forum on Advanced Replacement for LIRS

56 LIRS has been adopted in My. SQL l My. SQL is the most widely used relational database – 11 million installations in the world – The busiest Internet services use My. SQL to maintain their databases for high volume Web sites: google, You. Tube, wikipedia, facebook, Taobao… – LIRS is managing the buffer pool of My. SQL – The adoption is the most recent version (5. 1), November 2008.

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59 Infinispan (a Java-based Open Software) The data grid forms a huge in-memory cache being managed using LIRS BP-Wrapper is used to ensure lock-free

60 Concurrentlinkedhashmap as a Software Cache • Linked list structure (a Java class) Elements are Linked and managed using LIRS replacement policy. BP-Wrapper ensures lock contention-free http: //code. google. com/p/concurrentlinkedhashmap/wiki/Design

61 LIRS Principle in Hardware Caches l A cache replacement hardware implementation based on Re-Reference Interval prediction (RRIP) l l Presented in ISCA’ 10 by Intel Two bits are added to each cache line to measure reuse-distance in a static and dynamic way l Performance gains are up to 4 -10% l Hardware cost may not be affordable in practice.

62 Impact of Clock-Pro in OS and Other Systems l l Clock-pro has been adopted in Free. BSD/Net. BSD (open source Unix) Two patches in Linux kernel for users – Clock-pro patches in 2. 6. 12 by Rik van Riel – Peter. ZClock. Pro 2 in 2. 6. 15 -17 by Peter Zijlstra l Clock-pro is patched in Aparche Derby (a relational DB) l Clock-pro is patched in Open. LDAP (directory accesses)

65 Multi-core Cannot Deliver Expected Performance as It Scales Performance Reality Ideal Throughput = Concurrency/Latency -Exploiting parallelism - Exploiting locality “The Troubles with Multicores”, David Patterson, IEEE Spectrum, July, 2010 “Finding the Door in the Memory Wall”, Erik Hagersten, HPCwire, Mar, 2009 “Multicore Is Bad News For Supercomputers”, Samuel K. Moore, IEEE Spectrum, Nov, 2008

Challenges of Managing LLC in Multi-cores Ø 66 • Recent theoretical results about LLC in multicores – – Single core: optimal offline LRU algorithm exists Online LRU is k-competitive (k is the cache size) Multicore: finding an offline optimal LRU is NP-complete Cache partitioning for threads: an optimal solution in theory • System Challenges in practice – LLC lacks necessary hardware mechanism to control inter-thread cache contention • LLC share the same design with single-core caches – System software has limited information and methods to effectively control cache contention

67 OS Cache Partitioning in Multi-cores (HPCA’ 08) • Physically indexed caches are divided into multiple regions (colors). • All cache lines in a physical page are cached in one of those regions (colors). Physically indexed cache Virtual address virtual page number OS control Address translation Physical address physical page number page offset Page offset = OS can control the page color of a virtual page through address mapping (by selecting a physical page with a specific value in its page color bits). Cache address Cache tag Set index page color bits Block offset ……

68 Shared LLC can be partitioned into multiple regions Physical pages are grouped to different bins based on their page colors Physically indexed cache 1 2 3 4 … …… … i i+1 i+2 Process 1 … . . . 1 2 3 4 OS address mapping Shared cache is partitioned between two processes through OS … mapping. address … … …… … i Main memory space needs to be partitioned too (co-partitioning). i+1 …… i+2 … Process 2 … ……

69 Implementations in Linux and its Impact • Static partitioning – Predetermines the amount of cache blocks allocated to each running process at the beginning of its execution • Dynamic cache partitioning – Adjusts cache allocations among processes dynamically – Dynamically changes processes’ cache usage through OS page address re-mapping (page re-coloring) • Current Status of the system facility – Open source in Linux kernels – adopted as a software solution in Intel SSG in May 2010 – used in applications of Intel platforms, e. g. automation

Final Remarks: Why LIRS-related Efforts Make the Difference? 70 • Caching the most deserved data blocks – Using reuse-distance as the ruler, approaching to the optimal – 2 Q, LRU-k, ARC, and others can still cache non-deserved blocks • LIRS with its two-stack yields constant operations: O(1) – Consistent to LRU, but recording much more useful information • Clock-pro turns LIRS into reality in production systems – None of other algorithms except ARC have approximation versions • BP-Wrapper ensures lock contention free in DBMS • OS partitioning executes LIRS principle in LLC in multicores – Protect strong locality data, and control weak locality data

Acknowledgement to Co-authors and Sponsors 71 • Song Jiang – Ph. D. ’ 04 at William and Mary, faculty at Wayne State • Feng Chen – Ph. D. ’ 10 , Intel Labs (Oregon) • Xiaoning Ding – Ph. D. ‘ 10 , Intel Labs (Pittsburgh) • Qingda Lu – Ph. D. ’ 09 , Intel (Oregon) • Jiang Lin – Ph. D’ 08 at Iowa State, AMD • Zhao Zhang – Ph. D. ’ 02 at William and Mary, faculty at Iowa State • P. Sadayappan, CSE faculty • Continuous support from the National Science Foundation

73 Xiaodong Zhang : zhang@cse. ohio-state. edu http: //www. cse. ohio-state. edu/~zhang