NMOS FABRICATION 1 Processing is carried out on

NMOS FABRICATION 1. Processing is carried out on a thin wafer cut from a single crystal of silicon of high purity into which the required p-impurities are introduced as the crystal is grown.

2. A layer of silicon dioxide (Si 02), typically 1 μm thick, is grown all over the surface of the wafer to protect the surface, act as a barrier to dopants during processing.

3. The surface is now covered with a photo resist which is deposited onto the wafer and spun to achieve an even distribution of the required thickness.

4. The photo resist layer is then exposed to ultraviolet light through a mask which defines those regions into which diffusion is to take place together with transistor channels. Assume, for example, that those areas exposed to ultraviolet radiation are polymerized (hardened), but that the areas required for diffusion are shielded by the mask and remain unaffected

5. These areas are subsequently readily etched away together with the underlying silicon dioxide so that the wafer surface is exposed in the window defined by the mask

6. The remaining photoresist is removed and a thin layer of Si 02 (0. 1 jlm typical) is grown over the entire chip surface and then polysilicon is deposited on top of this to form the gate structure.

7. Further photo resist coating and masking allows the polysilicon to be patterned (as shown in Step 6) and then the thin oxide is removed to expose areas into which ntype impurities are to be diffused to form the source and drain as shown.

8. Thick oxide (Si 02) is grown over all again and is then masked with photoresist and etched to expose selected arcs of the polysilicon gate and the drain and source areas where connections (i. e. contact cuts) are to be made.

9. The whole chip then has metal (aluminum) deposited over its surface to a thickness typically of 1μm. This metal layer is then masked and etched to form the required interconnection pattern.

CMOS FABRICATION The p-well Process:

n. WELL PROCESS:

CMOS n. WELL processing steps

Cross sectional view of n-well CMOS inverter

The Twin-Tub Process: Steps in processing a wafer

Twin tub has the following steps v Tub formation v Thin oxide construction v Gate formation v Source and drain implantations v Contact cut definitions v Metallization

LATCH-UP IN CMOS CIRCUITS: Latch-up is a condition in which the parasitic components give rise to the establishment of low-resistance conducting paths between VDD and VSS with disastrous results. Careful control during fabrication is necessary to avoid this problem. Latch-up may be induced by glitches on the supply rails or by incident radiation. The mechanism involved may be understood by referring to Figure 2. 21, which shows the key parasitic components associated with a p-well structure in which an inverter circuit.

There are, in effect, two transistors and two resistances (associated with the p-well and with regions of the substrate) which form a path between VDD and VSS. If sufficient substrate current flows to generate enough voltage across RS to turn on transistor T 1, this will then draw current through Rp and, if the voltage developed is sufficient, T 2 will also turn on, establishing a self-sustaining low-resistance path between the supply rails. If the current gains of the two transistors are such that β 1 x β 2 > 1, latch-up may occur. Equivalent circuits are given in Figure 2. 22.

LATCHUP Latchup: positive feedback leading to VDD – GND short § Major problem for 1970’s CMOS processes before it was well understood Avoid by minimizing resistance of body to GND / VDD § Use plenty of substrate and well taps ls al it : 16 C u irc tf Pi SLIDE 21

LATCH-UP CIRCUIT FOR N-WELL PROCESS

LATCHUP PREVENTION Reducing the resistor values and reducing the gain of the parasitic transistors are the basis for eliminating latch up. This can be approached by v Latchup resistant CMOS process v Layout techniques

LATCH UP RESISTANT PROCESS (LAYOUT TECHNIQUES WILL BE PRESENTED IN THE FOLLOWING SECTION) : v Use of silicon starting-material with a thin epitaxial layer on top of a highly doped substrate. This decreases the value of the substrate resistor. v Retrograde well structure formed by a highly doped area at the bottom of the well and by lightly doping on the top portion of the well. This preserves good characteristics for the p-transistors and also reduces the well resistance deep in the well. v Increasing holding voltage above VDD such that latchup will not occur. v It is hard to reduce the betas (gains) of the bipolar transistors.

INTERNAL LATCHUP PREVENTION TECHNIQUE Reducing Rsubstrate and Rwell by substrate contact. The following rules are presented to achieve this goal. • Every well must have a substrate contact of the appropriate type. • Every substrate contact should be connected to metal directly to a supply pad. v Place substrate contacts as close as possible to the source connection of transistors and connect them to supply rails (i. e. , VSS for n-device, VDD for pdevices). v A very conservative rule would place one substrate contact for every supply connection. A less conservative rule is to place a substrate contact for every 510 transistors or every 25 -100μm. v Lay out n- and p- transistors with packing of n-device toward VSS and packing of p-device toward VDD

BICMOS A known deficiency of MOS technology lies in the limited load driving capabilities of MOS transistors. This is due to the limited current sourcing and current sinking abilities associated with both p- and ntransistors and although it is possible