NGR Next Generation Router Initial Design Review Shahzad
- Slides: 12
NGR: Next Generation Router Initial Design Review Shahzad Ali Xia Chen Brendan Howell Yu Zhong 18 -757 Initial Design Review
Specifications z. Minimum y 64 port OC-48, aggregate capacity of 160 Gbps, Fair Queuing. z. Extra features y. RED y. MPLS, Qo. S y. Multicast y. Scalability (higher port density) 10/7/2020 18 -757 Initial Design Review 2
Overall Design 16 Cards Switch One port on a Line card Transceiver Framer 10/7/2020 Cell buffer Network processor Scheduler + FQ Routing table 18 -757 Initial Design Review 3
Components z. Input Port processing (IPP) z. Buffers z. Switch Scheduling z. Output port processing z. Fair Queuing 10/7/2020 18 -757 Initial Design Review 4
Input Port Processing z. Line termination and data link processing z. Break variable length packet into fixed length z. Lookup routing information y. Process packets at "line speed” i. e. close to 5 million routing lookup per second. z. Do simple IP packet processing functions y. Decrease TTL, Checksum etc. y. MPLS or Hardware Filters 10/7/2020 18 -757 Initial Design Review 5
Possible Solutions for IPP z. Transceiver for line termination and PHY processing y. HFCT-5402 D by Agilent (HP) y. VSC 8140 by Vitesse z. Framer for fixed size cells y. VSC 9112 by Vitesse z. Network Processor y. IXP 1200 by Intel (Level One) y. APP 1200 and APP 1400 by Agere y. Generic micro-processor 10/7/2020 18 -757 Initial Design Review 6
Where to Queue? z. Input port y. Does not require high fabric speedup. y. OPP can be done at reasonable speeds y. Difficult to do output scheduling (FQ) z. Output port y. Easy to schedule packets on the link (FQ) y. Fabric and OPP have to have high speedup. 10/7/2020 18 -757 Initial Design Review 7
Buffers z. Our initial decision: y. Buffer packets on the input port y. Handle FQ at the input port (somehow) z. Use standard SDRAM for buffers y. PC-100 10 ns access latency y. Dimension buffer by simulation z. Buffers for each input port. 10/7/2020 18 -757 Initial Design Review 8
Switch Scheduling z We will simulate with various scheduling mechanisms including Multicast schemes. yi. SLIP, RR, FCFS, TARTAR (for multicast) z Virtual Output Queues to avoid HOL z Nominal Fabric speedup and priority classes. z Implement both Drop-tail and RED buffer schemes. z Local delivery of packets on the same line card. 10/7/2020 18 -757 Initial Design Review 9
Switch Fabric z. Shoot for 1024 x 1024 but backup is 64 x 64 z. Vitesse VSC 836 takes too long to configure!! y 13 cycles x 40 ns = 520 ns (1. 9 M Frames/sec) z. Use AMCC S 2018 17 x 17 in a 3 -stage CLOS network. z. Other options? 10/7/2020 18 -757 Initial Design Review 10
Output Port Processing and Scheduling z. Basic de-framing and physical level processing. z. FQ discipline y. WFQ y. W 2 FQ z. How do we do this with input buffering? y. What level of buffering do we require at the output ports? 10/7/2020 18 -757 Initial Design Review 11
Plan of Action z Decide on IPP and Network Processor. z Concentrate on switch fabric choice. z Analyze switch scheduling schemes. z Try to implement FQ with input port buffers. z Implement RED and Drop Tail. z Develop a simulator for the switch. z Experimentally determine the buffer size. 10/7/2020 18 -757 Initial Design Review 12
