NAND Gate Based Latch Transitions A 0 0

NAND Gate Based Latch Transitions A 0 0 1 1 B (AB)’ 0 1 1 1 0 0 S A 1 1 0 Q 0 Clk 1 0 R 0 1 Q B 1) Latched, initial state Q =1 0 S A Clk 1 1 0 Q 0 ->1 1 R 0 1 0 Q B 2) Latched to transparent, Clk: 0 ->1, no change in Q, neither S nor R are asserted

NAND Gate Based Latch Transitions A 0 0 1 1 B (AB)’ 0 1 1 1 0 0 S Clk 1 A 0 ->1 1 ->0 Q 1 1 ->0 R 0 ->1 1 ->0 B 0 ->1 Q 3) Transparent, reset is asserted, R: 0 ->1, B: 1 ->0, Q’: 0 ->1, Q: 1 ->0, Q Flips to 0 1 S A Clk 1 0 1 Q 1 0 R 1 ->0 0 ->1 1 Q B 4 a) Transparent, R: 1 ->0, B: 0 ->1, no change in Q

NAND Gate Based Latch Transitions A 0 0 1 1 B (AB)’ 0 1 1 1 0 0 S A Clk 1 0 1 Q 1 ->0 0 1 R 0 ->1 B 1 Q 4 b) Starting from 3), transparent to latched, CLK: 1 ->0, B: 0 ->1, no change In Q 0 S A Clk 1 0 1 Q 0 0 R 1 ->0 1 1 B 5) Latched, R: 1 ->0, no change in Q Q

NAND Gate Based Latch Transitions A 0 0 1 1 B (AB)’ 0 1 1 1 0 0 ->1 S A 1 0 1 Q 0 Clk 0 R 0 1 1 Q B 6) Latched, S: 0 ->1, no Change In Q 1 S Clk 1 ->0 A 1 ->0 0 ->1 Q 0 ->1 R 0 1 1 ->0 Q B 7) Latched to transparent, Clk: 0 ->1, A: 1 ->0, Q: 0 ->1, Q’: 1 ->0, Q Sets to 1

NAND Gate Based Latch Transitions A 0 0 1 1 B (AB)’ 0 1 1 1 0 1 S Clk 0 ->1 A 0 1 Q 1 ->0 1 R 0 1 0 Q B 8) Transparent to latched, CLK: 1 ->0, A: 0 ->1, no change in Q

Rising Edge Triggered D Flip-Flop Transitions A 0 0 1 1 B (AB)’ 0 1 1 1 0 0 1 1 1 TRANSPARENT CLK=0 Holds P 1=1 1 1 2 0 P 3 P 1 5 1 Clock 0 Q LATCHED 0 1 0 0 1 3 1 P 2 6 TRANSPARENT CLK=0 Holds P 2=1 1 D 0 4 0 P 4 1) Initial state, latched, Q=0 1 Q

Rising Edge Triggered D Flip-Flop Transitions A 0 0 1 1 B (AB)’ 0 1 1 1 0 0 1 1 ->0 1 P 3 1 1 ->0 2 0 ->1 P 1 1 ->0 Clock 5 0 ->1 Q 0 ->1 1 ->0 0 ->1 0 1 3 P 2 6 1 ->0 Q 1 D 1 4 0 P 4 2) Rising clock edge, Clk: 0 ->1, loads the value on D so Q=1=D

Rising Edge Triggered D Flip-Flop Transitions A 0 0 1 1 B (AB)’ 0 1 1 1 0 0 ->1 1 0 1 P 3 1 0 2 1 P 1 5 0 Clock 1 Q 1 1 0 ->1 1 3 P 2 6 0 Q 1 D 1 ->0 4 0 ->1 P 4 3) D changes, doesn’t change Q, Q only changes on the rising edge of Clk

Rising Edge Triggered D Flip-Flop Transitions A 0 0 1 1 B (AB)’ 0 1 1 1 0 ->1 1 ->0 P 3 1 ->0 0 ->1 2 1 ->0 P 1 5 0 Clock 1 1 ->0 1 0 ->1 1 ->0 1 1 3 P 2 6 0 1 D Q 0 4 1 P 4 4) Clk goes low, Q doesn’t change and is latched Q

Rising Edge Triggered D Flip-Flop Transitions A 0 0 1 1 B (AB)’ 0 1 1 1 0 P 3 0 1 2 0 P 1 5 0 Clock 1 Q 0 1 1 1 0 1 3 P 2 6 0 Q 1 D 0 4 1 P 4 5) No signal changes Flip-flop is loaded with Q = 1