Nab DAQ High Voltage Chris Crawford Aaron Sprow

Nab DAQ + High Voltage Chris Crawford Aaron Sprow

Outline • Overview – DAQ requirements / selection process • NI DAQ system – Architecture and hardware – Local and global triggers – Interfaces: GUI / Slow control / Postprocessor • Contract with NI – SOW: firmware/software development – Hardware: 2 -phased purchase + warranty • Faraday cage

DAQ System Requirements Event Structure 100 -750 ke. V electron, 100 ps systematic, 2 ke. V resolution, 1. 6 k. Hz singles 30 ke. V (HV) proton, 12– 40 μs TOF delay, 10 ns resolution, 200 Hz coinc. Data rate Coincidence in adjacent pixel (7/127); accidentals from decay <1% in 40 us 256 ch digitizer 100 -250 MS/s sample rate, 14 -16 bit ADC * 14 pixels * 4 us * 2 * 600 Hz = 34 MB/s = 20 TB/week w/o compression Trigger scheme Trigger L 1) DIGITIZER threshold, L 2) FPGA readout, L 3) CPU storage levels: separate pixels single particle decay coincidences detector 30 k. V ADC digitizer FPGA (L 1) readout (L 3) trigger logic FPGA (L 2) hits PXI bus trigger lines rear I/O module fiber optics 3

DAQ Schedule ✔ July 2013: development of test firmware and software ✔ Aug 2013 – Apr 2014: testing of prototype systems at LANL ✔ July 2014: hardware vendor selection: National Instruments MILESTONE for Q 3 2014, achieved in Q 2 Oct 2014: purchase order for complete mini-system (48 channels) Dec 2014: development at LANL UCNB on prototype detector/preamps Mar 2015: purchase order for remaining digitizer cards (208 channels) detector 30 k. V ADC digitizer FPGA (L 1) readout (L 2/L 3) readout (L 3) trigger logic FPGA (L 2) hits PXI bus trigger lines rear I/O module fiber optics 4

Hardware specifications / test results • FGPA processing power important for advanced trigger filters and global trigger logic • Memory / bandwidth required for CPU trigger logic CONCLUSION: the essential discriminator for Nab is NOT online energy resolution, but: CUSTOM TRIGGER and LOGIC DEVELOPMENT

Hardware Decision: NI-5171 R • 8 channel, 14 -bit ADCs at 250 MS/s ± 0. 2 – 5 V pp, 50 Ω input single-ended • 8 digital I/O at 50 MHz • Kintex-7 410 T FPGA • 12 Gb DDR 3 = 428 ms/ch • >3. 2 GB/s to PXIe • • • 10 MHz OCXO clock over fiber 12 GB/s PXIe backplane with clock/trig lines Fiber optic PXIe -PCIe bridge

Typical DAQ New Approach

Online Triggering Algorithms • High efficiency detection of events – Cusp-like shape (step response amplification) • Background noise cancellation – Symmetric (Gaussian noise cancellation) – Flat-top (finite rise time) + long average time for trigger – Baseline restoration (exponential constant) • Recursive, real-time implementation

Basic Trapezoid Filter Implementation V. T. Jordanov and G. F. Knoll

Higher-order Response Function

Implementation of Cusp Filter Example Can adapt to actual waveforms using FFT!

Global Trigger Logic • All coincidence logic in simple C loop • At 50 k. Hz singles (2 ev/40 us), CPU load = 0. 8%

Control/GUI • Features – – Pixel map to actively track pixels: https: //db. tt/wix 8 Sy 64 Online spectra and waveforms Event/data rates Local/remote start and stop

Post-Processing Difference between trigger and post-processing Data fit as it comes in (another computer/GPU) Linear/nonlinear fits (pulse height + exponential decay + pedestal + time) Will fit to optimized template pulse accounting for background noise spectrum Fit Functions Waveform Weighted Response. Functions Coefficients c 2

Statement of Work $23. 8 k (100 hr) • Assisting with the development and documentation of system level requirements • Providing architecture/code reviews • Design and implementation of the synchronization aspects of the system • Design and implementation of the data storage/retrieval mechanisms

Hardware and Service Contract Cost escalation to date: Baseline NI original: Final quote: $282 k $292 k + 13 k $290 k + 34 k 1 yr warranty + 1 spare + fiber hardware+NRE + 3 yr warranty (67%disc) hardware+NRE + 5 yr warranty (36%disc) Will need to use contingency to purchase warranty. Will put “operation at HV” working into Statement of Work will require extensive negotiation with NI to include in warranty contract NI “Big Physics” will purchase 1 digitizer for development and quick turnaround for warranty repair Purchase sequence: (delivery date, 90% confidence level) 2014 -11 -21: Initial hardware, only 6 modules 2015 -01 -23: Nonrecurring engineering: 2015 -03 ? Remaining 26 modules $75347. 65 $23800. 00 $225752. 47 Will purchase and develop initial system for development / testing @ LANL / UCNB Will purchase remaining modules after complete verification of specifications.

High Voltage Cage • Requirements: – Low capacitance to protect electronics – Capacity: 1 PXIe crate Preamp power supplies LN 2 dewar? , ? ? ? • Reference designs: – – LANL Uva a. CORN ASPECT