n CHAPTER 5 n Sequential Circuits Latches FlipFlops
- Slides: 46
n CHAPTER 5: n Sequential Circuits: Latches & Flip-Flops
Sequential Circuit n There are two types of sequential circuits: Ø Synchronous (latch mode) sequential circuit: the behavior can be defined from knowledge of its signal at discrete instants of time. This type of circuits achieves synchronization by using a timing signal called the clock. Ø Asynchronous (fundamental mode) sequential circuit: the behavior is dependent on the order of input signal changes over continuous time, and output can change at any time (clockless).
Sequential Circuit Models
Sequential Circuit Models
Sequential Circuit Models
Several Subsets of the general sequential circuit model E=f(I) St+1=f(St, E) O=g(St) sequential delay model
Several Subsets of the general sequential circuit model Simple sequential counter model E=f(St) St+1=f(St, E) O=g(St)
Several Subsets of the general sequential circuit model E=f(I, St) St+1=f(St, E) Moore sequential circuit model O=g(St) E=f(I, St) St+1=f(St, E) Mealy sequential circuit model O=g(I, St)
Alternatives in FF choice n Type of FF Ø Ø n SR D JK T D Q CLK positive edge-triggered flip-flop negative edge-triggered flip-flop Type of triggering Ø Ø Ø Untriggered (asynchronous) Level-triggered (C=1) Edge-triggered (rising or falling edge of C) D Q G CLK transparent (level-sensitive) latch
Clock Signal Clock generator: Periodic train of clock pulses
S’R’ Latch (NAND version) S’ R’ Q Q’ S’ 0 0 1 1 R’ Qn+1 1 0 0 1 Qn Qn+1’ 1 Disallowed 0 Set 1 Reset Qn’ Hold
S’R’ Latch (NAND version) Truth table Characteristic Equation Qn+1=S+R’Qn S’+R’=1
SR latch (NOR version) -- SR: “set-reset”, bi-stable element with two extra inputs; note the “undefined” output for S=R=1.
SR latch (NOR version) Characteristic Equation Qn+1=S+R’Qn SR=0
SR Latches
SR Latch Simulation
SR Latch Simulation R ’ S’ R’ S’ Q Q’
SR Latch with Clock signal Latch is sensitive to input changes ONLY when C=1 Characteristic Equation Qn+1=S+R’Qn SR=0
SR Latch with Clock signal CP R S Q Q’ hold
D Latch n One way to eliminate the undesirable indeterminate state in the RS flip flop is to ensure that inputs S and R are never 1 simultaneously. This is done in the D latch: Characteristic Equation Qn+1=S+R’Qn=D+D’’Qn=D
D Latch CP D Q
JK Latch When EN=1 R’=(KQn)’ S’=(JQn’)’ So : Qn+1=S+R’Qn=JQn’+(KQn)’ Qn = JQn’+K’ Qn Qn+1=JQn’+K’Qn S’+R’=(JQn’)’+(KQn)’ =J’+Qn+K’+Qn’ =1
JK Latch
JK Latch CP J K Q Q’
JK Latch’s oscillation See Figure 5. 21(P 189)
JK master-slave Latch
JK master-slave Latch
JK master-slave Latch
JK master-slave Latch
Edge Triggered Flip-flops Page 193: Figure 5. 29
T Latch Qn+1=JQn’+K’Qn =TQn’+T’Qn
T Latch Conclusion: (CP clock ) When T = 0 , Qt+1 = Qt When T = 1 , Qt+1 = Qt’
Characteristic equations compare
Simple counters n Devide by 2, 4, 8 Counters
Simple counters n Devide-by 4 Counter
Simple counters n Devide-by 8 Counter
Johnson Counter n Page 204: Figure 5. 64
Johnson Counter n Page 204: Figure 5. 65
Ring Counter n Page 204: Figure 5. 66, Figure 5. 67
Ring Counter n Page 205: Figure 5. 67
Control Signal Generation by Decoding Counter Outputs n Using counter to realize following control signals:
Control Signal Generation by Decoding Counter Outputs E 1 = f(Q 3, Q 2, Q 1, Q 0) = m(2, 3, 8, 9, 10, 11) E 2 = f(Q 3, Q 2, Q 1, Q 0) = m(5) E 3 = f(Q 3, Q 2, Q 1, Q 0) = m(9)
Control Signal Generation by Decoding Counter Outputs
A Counter Application: Digital Clock
Homework P 237 4, 6 n P 238 12, 18 n P 241 33. n
- Latches
- Flipflops
- The interrupt is an example of edge triggered
- What is the difference between latches and flip flops
- Sr latch cmos
- Lach sr
- D flip flop truth table
- Non bistable sequential circuits
- Sequential circuit analysis
- Rangkaian logika sekuensial
- Finite state machine sequential circuits
- Continues
- Analysis of sequential circuits
- Non bistable sequential circuits
- Sequential circuits prelude
- Sequential circuits
- State diagram
- Analysis of synchronous sequential circuits
- Synthesis of synchronous sequential circuits
- 74ls112
- Mealy and moore sequential circuits
- State diagram
- What is a parallel circuit in physics
- Fundamentals of electric circuits chapter 4 solutions
- Electric current
- Conceptual physics chapter 35
- Chapter 23 series and parallel circuits study guide answers
- Chapter 20 electric circuits
- Chapter 17 section 3 circuits answer key
- The circuit chapter 9
- Fundamentals of electric circuits chapter 7 solutions
- Chapter 35 electric circuits answers
- Circuits-current worksheet answers
- 2-to-1 multiplexer
- Chapter 35 electric circuits
- First order circuit
- Sequential intercept model template
- Sequential organization
- Sequential representation of binary tree
- Dave clausen
- Climax graphic organizer
- Sequential vs longitudinal study
- Sequential linear menus
- Module 1. stl sequential containers
- Call and return architecture diagram
- Sequential search algorithm
- Spld cpld fpga