Multiplication Design 1 0 Arithmetic 1 Multiplicand Shift

Multiplication Design 1. 0 Arithmetic 1 Multiplicand Shift left 64 bits Multiplier 64 -bit ALU Shift right 32 bits Product Control test Write 64 bits The natural (by-hand) algorithm for integer multiplication leads to the design above. However, this requires additional 64 -bit hardware for the ALU that would not be needed for implementing integer addition… Computer Science Dept Va Tech February 2008 Intro Computer Organization © 2006 -08 Mc. Quain

CS 2504 Arithmetic 2 The diagram at left corresponds to (and inspires) the previous design. If each step took 1 clock cycle, multiplying two 32 -bit operands would take nearly 100 clock cycles. QTP: what's the cost of integer addition? Computer Science Dept Va Tech February 2008 Intro Computer Organization © 2006 -08 Mc. Quain

Multiplication 2. 0 Arithmetic 3 Multiplicand 32 bits 32 -bit ALU Shift right Product Control test Write 64 bits The revision here removes the need for a 64 -bit ALU (as well as the 32 -bit register for the multiplier). How does this work? Computer Science Dept Va Tech February 2008 Intro Computer Organization © 2006 -08 Mc. Quain

Multiplication 2. 0 Arithmetic 4 32 -bit ALU Product Shift right Multiplier Control test 64 bits The multiplier is placed in the low 32 bits of the 64 -bit Product register. As the product is formed, beginning in the top half of that register, the shifting of the multipler gradually removes it "just-in-time". QTP: how does the operation count compare with the first version? Computer Science Dept Va Tech February 2008 Intro Computer Organization © 2006 -08 Mc. Quain