Multiple Clock Domains Arvind Computer Science Artificial Intelligence

Multiple Clock Domains Arvind Computer Science & Artificial Intelligence Lab Massachusetts Institute of Technology Based on material prepared by Bluespec Inc March 7, 2008 http: //csg. csail. mit. edu/6. 375 L 12 -1

802. 11 Transmitter Overview Clock frequencies: f/52 f headers Controller data f/13 Scrambler Encoder Interleaver Mapper IFFT Cyclic Extend The relative clock frequency of each block is based on its internal architecture and the overall performance requirement March 7, 2008 http: //csg. csail. mit. edu/6. 375 2

Synthesis results for different microachitectures Design Area (mm 2) CLK Period Throughput (1 symbol) Latency Comb. 1. 03 15 ns Pipelined 1. 46 7 ns 21 ns Folded 0. 83 8 ns 24 ns S Folded 1 Radix 0. 23 8 ns 408 ns Nirav Dave Mike Pellauer Man C Ng Will have to run ~20 times faster for the same throughput TSMC. 13 micron; numbers reported are before place and route. Single radix-4 node design is ¼ the size of combination design but still meets the throughput requirement easily; clock can reduced to 15 to 20 Mhz March 7, 2008 http: //csg. csail. mit. edu/6. 375 3

BSV point of view Automate the simplest things Make it easy to do simple things Make it safe to do the more complicated things March 7, 2008 http: //csg. csail. mit. edu/6. 375 4

The simplest case Only one clock Need never be mentioned in BSV source n (Note: hasn’t been mentioned in any examples so far!) Synthesized modules have an input port called CLK This is passed to all interior instantiated modules March 7, 2008 http: //csg. csail. mit. edu/6. 375 5

Multiple Clock Domains in Bluespec The Clock type, and functions Clock families Making clocks Moving data across clock domains Revisit the 802. 11 a Transmitter March 7, 2008 http: //csg. csail. mit. edu/6. 375 6

The Clock type Clock is an ordinary first-class type May be passed as parameter, returned as result of function, etc. Can make arrays of them, etc. Can test whether two clocks are equal Clock c 1, c 2; Clock c = (b ? c 1 : c 2); March 7, 2008 // b must be known at compile time http: //csg. csail. mit. edu/6. 375 7

The Clock type Conceptually, a clock consists of two signals n n an oscillator a gating signal In general, implemented as two wires If ungated, oscillator is running n March 7, 2008 Whether the oscillator is running when it is gated off depends on implementation library —tool doesn’t care http: //csg. csail. mit. edu/6. 375 8

Instantiating modules with non-default clocks Example: instantiating a register with explicit clock Clock c = … ; Reg# (Bool) b <- mk. Reg (True, clocked_by c); Modules can also take clocks as ordinary arguments, to be fed to interior module instantiations March 7, 2008 http: //csg. csail. mit. edu/6. 375 9

The clock. Of() function May be applied to any BSV expression, and returns a value of type Clock If the expression is a constant, the result is the special value no. Clock The result is always well-defined n March 7, 2008 Expressions for which it would not be welldefined are illegal http: //csg. csail. mit. edu/6. 375 10

The clock. Of() function Example Reg# (UInt# (17)) x <- mk. Reg (0, clocked_by c); let y = x + 2; Clock c 1 = clock. Of (x); Clock c 2 = clock. Of (y); c, c 1 and c 2 are all equal They may be used interchangeably for all purposes March 7, 2008 http: //csg. csail. mit. edu/6. 375 11

A special clock Each module has a special “default” clock The default clock will be passed to any interior module instantiations (unless otherwise specified) It can be exposed in any module as follows: Clock c <- expose. Current. Clock; March 7, 2008 http: //csg. csail. mit. edu/6. 375 12

Multiple Clock Domains in Bluespec The Clock type, and functions √ Clock families Making clocks Moving data across clock domain Revisit the 802. 11 a Transmitter March 7, 2008 http: //csg. csail. mit. edu/6. 375 13

Clock families All clocks in a “family” share the same oscillator n They differ only in gating If c 2 is a gated version of c 1, we say c 1 is an “ancestor” of c 2 n If some clock is running, then so are all its ancestors The functions is. Ancestor(c 1, c 2) and same. Family(c 1, c 2) are provided to test these relationships n March 7, 2008 Can be used to control static elaboration (e. g. , to optionally insert or omit a synchronizer) http: //csg. csail. mit. edu/6. 375 14

Clock family discipline All the methods invoked by a rule (or by another method) must be clocked by clocks from one family n The tool enforces this There is no need for special domaincrossing logic when the clocks involved are from the same family n March 7, 2008 It’s all handled by implicit conditions http: //csg. csail. mit. edu/6. 375 15

Clocks and implicit conditions Each action is implicitly guarded by its clock’s gate; this will be reflected in the guards of rules and methods using that action n n So, if the clock is off, the method is unready So, a rule can execute only if all the methods it uses have their clocks gated on This doesn’t happen for value methods n March 7, 2008 So, they stay ready if they were ready when the clock was switched off http: //csg. csail. mit. edu/6. 375 16

Clocks and implicit conditions Example: FIFO #(Int #(3)) f <- mk. FIFO (clocked_by c); If c is switched off: n n March 7, 2008 f. enq, f. deq and f. clear are unready f. first remains ready if the fifo was nonempty when the clock was switched off http: //csg. csail. mit. edu/6. 375 17

The clocks of methods and rules Every method, and every rule, has a notional clock For methods of primitive modules (Verilog wrapped in BSV): n Their clocks are specified in the BSV wrappers which import them For methods of modules written in BSV: n n n A method’s clock is a clock from the same family as the clocks of all the methods that it, in turn, invokes The clock is gated on if the clocks of all invoked methods are gated on If necessary, this is a new clock The notional clock for a rule may be calculated in the same way March 7, 2008 http: //csg. csail. mit. edu/6. 375 18

Multiple Clock Domains in Bluespec The Clock type, and functions √ Clock families √ Making clocks Moving data across clock domain Revisit the 802. 11 a Transmitter March 7, 2008 http: //csg. csail. mit. edu/6. 375 19

Making gated clocks Bool b = … ; Clock c 0 <- mk. Gated. Clock (b); c 0 is a version of the current clock, gated by b n c 0’s gate is the gate of the current clock AND’ed with b The current clock is an ancestor of c 0 March 7, 2008 http: //csg. csail. mit. edu/6. 375 20

Making gated clocks Bool b = … ; Clock c 0 <- mk. Gated. Clock (b); Bool b 1 = …; Clock c 1 <- mk. Gated. Clock (b 1, clocked_by c 0); c 1 is a version of c 0, gated by b 1 n and is also a version of the current clock, gated by (b && b 1) current clock, c 0 and c 1 all same family current clock and c 0 both ancestors of c 1 March 7, 2008 http: //csg. csail. mit. edu/6. 375 21

More Clock constructors mk. Gated. Clock n (Bool new. Cond) mk. Absolute. Clock n (Integer start, Integer period); mk. Clock. Divider n March 7, 2008 #(Integer divider) ( Clock. Divider. Ifc clks ) http: //csg. csail. mit. edu/6. 375 22

Clock Dividers interface Clock. Divider. Ifc ; interface Clock fast. Clock ; // original clock interface Clock slow. Clock ; // derived clock method Bool clock. Ready ; endinterface module mk. Clock. Divider #( Integer divisor ) ( Clock. Divider. Ifc ifc ) ; March 7, 2008 http: //csg. csail. mit. edu/6. 375 23

Clock Dividers No need for special synchronizing logic The clock. Ready signal can become part of the implicit condition when needed March 7, 2008 http: //csg. csail. mit. edu/6. 375 24

Multiple Clock Domains in Bluespec The Clock type, and functions √ Clock families √ Making clocks √ Moving data across clock domains Revisit the 802. 11 a Transmitter March 7, 2008 http: //csg. csail. mit. edu/6. 375 25

Moving Data Across Clock Domains Data moved across clock domains appears asynchronous to the receiving (destination) domain Asynchronous data will cause meta-stability The only safe way: use a synchronizer clk d q March 7, 2008 Setup & hold violation Meta-stable data http: //csg. csail. mit. edu/6. 375 26

Synchronizers Good synchronizer design and use reduces the probability of observing meta -stable data Bluespec delivers conservative (speed independent) synchronizers User can define and use new synchronizers Bluespec does not allow unsynchronized crossings (compiler static checking error) March 7, 2008 http: //csg. csail. mit. edu/6. 375 27

2 - Flop Synchronizer Most common type of (bit) synchronizer FF 1 will go meta-stable, but FF 2 does not look at data until a clock period later, giving FF 1 time to stabilize Limitations: n n When moving from fast to slow clocks data may be overrun Cannot synchronize words since bits may not be seen at same time s. DIN FF 0 FF 1 s. Clk March 7, 2008 http: //csg. csail. mit. edu/6. 375 FF 2 d. D_OUT d. Clk 28

Bluespec’s 2 -Flop Synchronizer mk. Sync. Bit send() FF 0 FF 1 FF 2 s. Clk read() d. Clk interface Sync. Bit. Ifc ; method Action send ( Bit#(1) bit. Data ) ; method Bit#(1) read () ; endinterface The designer must follow the synchronizer design guidelines: n n March 7, 2008 No logic between FF 0 and FF 1 No access to FF 1’s output http: //csg. csail. mit. edu/6. 375 29

Small Example Up/down counter, where direction signal comes from separate domain. Registers: Reg# (Bit#(1)) up_down_bit <mk. Reg(0, clocked_by ( read. Clk ) ); Reg# (Bit# (32)) cntr <- mk. Reg(0); // Default Clk The Rule (attempt 1): rule countup ( up_down_bit == 1 ) o ; ck g l n i C s cntr <= cntr + 1; l s a g ro endrule e C l l March 7, 2008 http: //csg. csail. mit. edu/6. 375 I ain m o D 30

Adding the Synchronizer Sync. Bit. Ifc sync <- mk. Sync. Bit( read. Clk, read. Rst, current. Clk ) ; Split the rule into two rules where each rule operates in one clock domain clocked by read. Clk rule transfer ( True ) ; sync. send ( up_down_bit ); endrule clocked by current. Clk rule countup ( sync. read == 1 ) ; cntr <= cntr + 1; endrule March 7, 2008 http: //csg. csail. mit. edu/6. 375 31

Full Example module mk. Top. Level( Clock read. Clk, Reset read. Rst, Top ifc ); Reg# (Bit# (1)) up_down_bit <- mk. Reg(0, clocked_by(read. Clk), reset_by(read. Rst)) ; Reg# (Bit# (32)) cntr <- mk. Reg (0) ; // Default Clocking Clock current. Clk <- expose. Current. Clock ; Sync. Bit. Ifc sync <- mk. Sync. Bit ( read. Clk, read. Rst, current. Clk ) ; rule transfer ( True ) ; sync. send( up_down_bit ); endrule countup ( sync. read == 1 ) ; cntr <= cntr + 1; endrule March 7, 2008 http: //csg. csail. mit. edu/6. 375 32

Other Synchronizers Pulse Synchronizer Word Synchronizer FIFO Synchronizer Asynchronous RAM Null Synchronizer Reset Synchronizers Documented in Reference Guide March 7, 2008 http: //csg. csail. mit. edu/6. 375 33

Multiple Clock Domains in Bluespec The Clock type, and functions √ Clock families √ Making clocks √ Moving data across clock domains √ Revisit the 802. 11 a Transmitter March 7, 2008 http: //csg. csail. mit. edu/6. 375 34

802. 11 Transmitter Overview Clock frequencies: f/52 f headers f/13 Controller March 7, 2008 data Scrambler Encoder Interleaver Mapper IFFT Cyclic Extend http: //csg. csail. mit. edu/6. 375 35

The Transmitter module mk. Transmitter(Transmitter#(24, 81)); function Action stitch(Action. Value#(a) x, function Action f(a v)); action let v <- x; f(v); endaction endfunction What is the let controller <- mk. Controller(); clock domain ? let scrambler <- mk. Scrambler_48(); let conv_encoder <- mk. Conv. Encoder_24_48(); let interleaver <- mk. Interleaver(); let mapper <- mk. Mapper_48_64(); let ifft <- mk. IFFT_Pipe(); let cyc_extender <- mk. Cyclic. Extender(); rule controller 2 scrambler(True); stitch(controller. get. Data, scrambler. from. Control); endrule. . . more rules. . . March 7, 2008 http: //csg. csail. mit. edu/6. 375 36

The Transmitter module mk. Transmitter(Transmitter#(24, 81)); let clockdiv 13 <- mk. Clock. Divider(13); let. . . clockdiv 52 <- mk. Clock. Divider(52); let clk 13 th = clockdiv 13. slow. Clock; let clk 52 nd = clockdiv 52. slow. Clock; let reset 13 th <- mk. Async. Reset. From. CC(0, clk 13 th); let reset 52 nd <- mk. Async. Reset. From. CC(0, clk 52 nd); let controller <- mk. Controller(); How should we let scrambler <- mk. Scrambler_48(); 1. Generate these let conv_encoder <- mk. Conv. Encoder_24_48(); clocks? let interleaver <- mk. Interleaver(); 2. Pass them to let mapper <- mk. Mapper_48_64(); modules let ifft <- mk. IFFT_Pipe(); let cyc_extender <- mk. Cyclic. Extender(); rule controller 2 scrambler(True); stitch(controller. get. Data, scrambler. from. Control); endrule March 7, 2008 http: //csg. csail. mit. edu/6. 375 37

The Transmitter (after) module mk. Transmitter(Transmitter#(24, 81)); let let let What about rules domain clockdiv 13 <- mk. Clock. Divider(13); involving clockdiv 52 <- mk. Clock. Divider(52); crossing? clk 13 th = clockdiv 13. slow. Clock; clk 52 nd = clockdiv 52. slow. Clock; reset 13 th <- mk. Async. Reset. From. CC(0, clk 13 th); reset 52 nd <- mk. Async. Reset. From. CC(0, clk 52 nd); let controller <- mk. Controller(clocked_by clk 13 th, reset_by reset 13 th); let scrambler <- mk. Scrambler_48(… " …); let conv_encoder <- mk. Conv. Encoder_24_48 (… " …); let interleaver <- mk. Interleaver (… " …); let mapper <- mk. Mapper_48_64 (… " …); let ifft <- mk. IFFT_Pipe(); let cyc_extender <- mk. Cyclic. Extender(clocked_by clk 52 nd, …); rule controller 2 scrambler(True); stitch(controller. get. Data, scrambler. from. Control); endrule. . . more rules. . . March 7, 2008 http: //csg. csail. mit. edu/6. 375 38

Clock Domain Crossing rule mapper 2 ifft(True); stitch(mapper. to. IFFT, ifft. from. Mapper); endrule ? ? ? rule mapper 2 ifft(True); let x <- mapper. to. IFFT(); ifft. from. Mapper(x) endrule Different methods in an action are on different clocks – not legal without synchronizers March 7, 2008 http: //csg. csail. mit. edu/6. 375 39

Clock Domain Crossing rule mapper 2 ifft(True); let x <- mapper. to. IFFT(); ifft. from. Mapper(x) endrule split let m 2 ifft. FF <mk. Sync. FIFOTo. Fast(2, clockdiv 13, reset 13 th); rule mapper 2 fifo(True); stitch(mapper. to. IFFT, m 2 ifft. FF. enq); Endrule fifo 2 ifft(True); stitch(pop(m 2 ifft. FF), ifft. from. Mapper); endrule March 7, 2008 http: //csg. csail. mit. edu/6. 375 40

Similarly for IFFT to Cyclic. Ext let ifft 2 ce. FF <mk. Sync. FIFOTo. Slow(2, clockdiv 52, reset 52 nd); rule ifft 2 ff(True); stitch(ifft. to. Cyclic. Extender, ifft 2 ce. FF. enq); endrule ff 2 cyclic. Extender(True); stitch(pop(ifft 2 ce. FF), cyc_extender. from. IFFT); endrule March 7, 2008 http: //csg. csail. mit. edu/6. 375 41

Did not work. . . stoy@forte: ~/examples/80211$ bsc -u -verilog Transmitter. bsv Error: ". /Interfaces. bi", line 62, column 15: (G 0045) Method get. From. MAC is unusable because it is connected to a clock not available at the module boundary. The method’s clock is internal! March 7, 2008 http: //csg. csail. mit. edu/6. 375 42

The Fix – pass the clocks out interface Transmitter#(type in. N, type out); method Action get. From. MAC(TXMAC 2 Controller. Info x); method Action get. Data. From. MAC(Data#(in. N) x); method Action. Value#(Msg. Complex. FVec#(out)) to. Analog. TX(); interface Clock endinterface March 7, 2008 clk. MAC; clk. Analog; http: //csg. csail. mit. edu/6. 375 43

Summary The Clock type, and type checking ensures that all circuits are clocked by actual clocks BSV provides ways to create, derive and manipulate clocks, safely BSV clocks are gated, and gating fits into Ruleenabling semantics BSV provides a full set of speed-independent data synchronizers, already tested and verified The user can define new synchronizers BSV precludes unsynchronized domain crossings March 7, 2008 http: //csg. csail. mit. edu/6. 375 44