MultiPhase Stackable Controllers For Non Portable Application Nancy

Multi-Phase, Stackable Controllers For Non- Portable Application Nancy Zhang Applications Engineer Computing Power Management 1

Agenda • • • Introduction TPS 40140 Dual Phase Stackable Controller TPS 40180 Single Phase Stackable Features New 4 -phase TPS 40140 EVM Performance Conclusions 2

Traditional Multiphase Buck Controller Advantages: • Exactly match the phase numbers required by applications Disadvantages: • Hard to re-use the design for different applications • No flexibility to expand the system for higher current requirement • Hard to layout for increased phase numbers 3

Stackable Buck Controller Solution Flexibility!! Advantages: • • Very flexible for system expansion Can easily stack with the same converter to achieve higher power Identical stackable design block reducing layout complexity Interleaved phases reduces input ripple for multiphase and multi-output applications Very good for universal power solution design Dynamic Phase Management Single part number easy for part number and production control Disadvantages: • None 4

Universal Stackable Building Blocks Build ANY size Power supply with just 2 parts !!!! TOOL BOX Single Phase Two Phase Tps 40180 Single phase Block Tps 40180 Tps 40140 Two phase Block Tps 40140 Dual Output Block 5

Multiphase - Single Output Single phase application (up to 25 A) Vin Vo Tps 40180 Single phase Block Vin Tps 40140 Two phase Block Vo or Tps 40180 Single phase Block COMP Vo CLKIO Tps 40180 Single phase Block 6

Multiphase - Single Output Three phase output application (up to 75 A) Vin Tps 40180 Single phase Block Vo Tps 40140 Two phase Block Four phase output application (up to 100 A) Vin Tps 40140 Two phase Block Vo 7

Multiple Output Rails Three Output Rails with Synchronization Vin Tps 40180 Single phase Block Vo 1 Vin Vo 2 Vo 3 Tps 40180 Single phase Block Vo 1 or Tps 40140 Dual Output Block Vo 2 Vo 3 8

TPS 40140 Dual-Phase Stackable Controller • • • • 1 V to 40 V Input Voltage Range • Supports multi bus rails Internal 5 V regulator • No need for external 5 Vbias 0. 7 V to 5. 8 V Output Voltage Range • Easy-to-use solution for voltage rails up to 40 A Dual-phase Interleaved up to 16 phases • Reduced Input, Output Ripple, Save input, output caps Programmable switching frequency up to 1 MHz • Optimized Efficiency and high power density 0. 5% 0. 7 V reference voltage • Tight Output Voltage Accuracy Current mode control with forced current sharing • Supports all MLCC Designs Support pre-biased outputs • No output glitch when loads are pre-charged Power sharing from different input voltage rail • Optimized input current from input rail True remote sense differential amplifier • Improve regulation and ease layout constrains Programmable input under voltage lockout • Flexibility design Resistive or Inductor DCR current sensing • Complete Control, power sequencing and system protection PGOOD, OCP, OVP, UVP • High Power Density, Excellent Thermal Performance 36 pin QFN Thermally Enhanced Package • • • Servers, Notebook/Netbook Computers Networking Equipment Telecommunications Equipment Graphic Cards and Internet Serves Low-voltage, Point-Of-Load Converters DC Power Distributed System 9 9

TPS 40140 Key Features Stackable!!! • • • Selectable Dual-Output or 2 -Phase Interleaved Operation, Stackable up to 16 Phases VDD From 4. 5 V to 15 V, With Internal 5 V Regulator VOUT From 0. 7 V to 5. 8 V True Remote Sensing Differential Amplifier Programmable Switching Frequency Up to 1 MHz/Phase Soft Start without/with Pre-biased Output Resistive Divider Sets Input Under voltage Lockout Resistive or Inductors DCR Current Sensing Peak Current Mode Control with Forced Current Sharing 10

Functional Diagram Phase 1 Driver Current Loop 1 Voltage Loop 1 COMPx Voltage Loop 2 Current Loop 2 Phase 2 Driver UVLOx Enable PHSEL CLKIO 11

Stackable Configurations • TPS 40140 can be stackable up to 16 phases with synchronization • One TPS 40140 is configured as master and the other chips are configured as slave • Three wire connections are required: CLKIO, COMP, PHSEL – CLKIO synchronize all the chips – COMP force the current balance – PHSEL provides the right phase information 12

Digital Synchronization Scheme PHSEL Pin: • There are two CLK schemes in the design, • The 6 -Phase CLK scheme is to achieve symmetric phase balance for a 6 phase or 12 -phase converter • The 8 -Phase CLK scheme is to achieve symmetric phase balance for 2, 4, 8, 16 phase converter 13

Digital Synchronization Scheme PHSEL Pin: 14

For example: 4 -phase Configuration PHSEL Pin: R • One phase resistor is connected to the PHSEL pin. • COMP and CLKIO pins are connected together • R=39. 2 k 15

For example: 3 -phase + Single Channel Configuration PHSEL Pin: • M_Ch 1, M_Ch 2 and S_Ch 1 construct the 3 -phase converter, S_Ch 2 is the single channel output • The master chip is not only voltage loop master, also the CLK master 16

Master/ Slave Operation CLKIO Pin: • Only three pins connection are required CLKIO, PHSEL, COMP (if current sharing) • Required a 10 k resistor connected from CLKIO to GND at Master- Slave operation When the master device is shut down or power off, the master CLKIO Pin goes to a high impedance state and there is no other active discharge part. The slave controllers looks at the CLKIO line to determine if the system is supposed to be running or not. A level below 0. 5 V on CLKIO is required. This 10 k resistor will ensure the CLKIO line falls to GND quickly 17

How to Disable Slave Modules? • Case 1: Parallel module without CLK distribution UVLO_CEx Pin – This application is mainly for module makers to do current sharing between modules with a single pin – The Pin is COMP for TPS 40140 application – One Module is set to master and the other modules are set to slave – The slave modules can be disabled by toggle the UVLO_CEx pin to GND. 18

How to Disable Slave Modules? • Case 2: for stackable applications with distributed CLK – To disable a slave module, the UVLO pin might not be directly pulled to GND that will also pull down the CLK VREG is turned off when Both UVLO pins are shorted to GND, then the CLK signal at CLKIO pin is also clamped to GND by D 1. 19

How to Disable Slave Modules? • Case 2: for stackable applications with distributed CLK – Method 1: Short one UVLO pin to GND while the other UVLO pin is still higher than 1. 5 V • This will shut down one channel and the other channel is still running or in standby mode(1. 5 V<UVLO<2 V) – Method 2: Held UVLO pin to be less than 2 V and higher than 1. 5 V, so the chip is in standby mode – Method 3: Ground the PHSEL pin of the master that will shut off all the slave modules, but the master is still running 20

How to Disable Slave Modules? • Case 2: for stackable applications with distributed CLK – Method 4: Use a jumper to disconnect the CLK to the slave module 21

How to Disable Slave Modules? • Case 2: for stackable applications with distributed CLK – Method 5: Turn off all the modules including the master by disconnect the PHSEL resistor string When SW 2 is open, the PHSEL Pin at the master will rise to be over 4 V and stop the master controller, hence the slave modules are also ceased. 22

Remote Sense VOUT and GSNS Pin • The unity gain differential amplifier has a high bandwidth to achieve improved regulation at user defined point of load and eases layout constrains. • The output voltage is sensed between the VOUT and GSNS pins. • The output voltage programming divider is connected to the output of the amplifier, the DIFFO pin. • Output 0. 7 V to 5. 8 V Voltage Range • You can bypass differential amplifier. Just short VSNS, GSNS to GND and leave DIFFO open 23

Output Voltage Setting DIFFO Pin • Two resistors, R 1 and RBIAS sets the output voltage Or DIFFO 24

Programmable Switching Frequency RT pin Master: • Frequency Setting by Rt • Can synchronize to external clock Slave: • RT pin tied to BP 5 • Where – f. PH is the phase switching frequency in k. Hz – Rt is in kΩ – There are two clock scheme in the chip called 8 -phase and 6 -phase scheme. – This equation gives the resistor selection for a 8 -phase scheme. For a 6 -phase scheme, the switching frequency is 4/3 times higher 25

Start Up and Shut Down Sequence It shows a typical start up with the VDD applied to the controller and then the UVLO -CEx being enabled. Shut down occurs when the VDD is removed. 26

Soft Start without Pre-biased Output TRKx Pin Master: • When UVLO_CEx is high and POR is cleared, the external soft start capacitor is charged with 12 -μA. • The rising voltage across the capacitor serves as a reference for the error amplifier • When TRK pin reaches the level of the reference voltage 0. 7 V, the converter’s output reaches the regulation point • When TRK pin voltage reaches 1. 4 V, the PGOOD pin goes high at this time. Slave: Tie TRKx pin to BP 5 for track function Css: Soft start capacitor in Farads Css connected from TRKx to GND Tss: Soft start time in seconds 27

Soft Start with Pre-biased Output TRKx Pin (Master): • When UVLO_CEx is high and POR is cleared, the external soft start capacitor is charged with 6 -μA until the TRK pin voltage is equal to the FB voltage • When the first PWM pulse occurs, the charging current is increased to 12 -μA. The rising voltage across the capacitor serves as a reference for the error amplifier • When TRK pin voltage reaches the level of the reference voltage 0. 7 V, the converter’s output reaches the regulation point • When TRK pin voltage reaches 1. 4 V, the PGOOD pin goes high at this time. • TRK pin voltage continues to rise to 2. 4 V which is clamped internally • If the pre-biased output voltage is greater than the regulation voltage, the controller does not start. 28

Soft Start with Pre-biased Output TRKx Pin: 29

Programmable Under Voltage Lock Out UVLO_CEx Pin • A resistor divider is connected to UVLO_CEx pins • Works as Enable function • The controller begins to work when the voltage on the UVLO_CEx pins is over 2 V. • The internal regulators are enabled when the voltage on the UVLO_CEx pins exceeds 1. 5 V, but switching commences when the voltage is 2 V. • This pin can be used to disable individual output for dual channel configuration; for master-slave configuration • UVLO hysteresis is only 40 m. V (Add three components to improve hysteresis to 1 V or 2 V) 30

UVLO Hysteresis Improved Circuit Add R 39(39. 2 k), D 5 and C 21(47 p. F) increase hysteresis from 40 m. V to 2 V LDRVx 31

Current Sensing Scheme CSx and CSRTx Pin • • TPS 40140 uses Inductor DCR or sensing resistor to obtaining current feedback information. DCR sensing is preferred as it is a lossless approach. If the R 1 C 1 time constant is matched to the L/DCR time constant, the voltage across C 1 will be equal to the voltage across DCR. A good starting point is equating C 1 = 0. 1 u. F. Then R 1 is calculated below. 32

Current Sensing Scheme CSx and CSRTx Pin • The peak voltage of Vc should not exceed ± 60 m. V because that is the maximum differential input voltage of the current sensing amplifier. • If the voltage Vc exceeds ± 60 m. V, a resistor can be added in parallel with C 1 to provide the voltage attenuation. The ratio 33

Current Sensing Scheme CSx and CSRTx Pin • As mentioned in the previous slide, the maximum differential input voltage of the CS amplifier is +/-60 m. V • The offset voltage is +/-2 m. V that will affect the current sharing accuracy – i. e. DCR=1 mohm, the sensing current tolerance is 2 A • The CS amplifier gain is typically 13 34

Sub-harmonics Consideration Inductor Selection • Sub-harmonics in peak current mode control systems can cause pulse skipping • To avoid sub-harmonics make the inductor current rising slope smaller than 2 x Vramp. • The following equation gives the L/DCR consideration achieve this Where Vin is input voltage, Vramp is the internal ramp voltage of 0. 5 V, and Ac is the current sensing amplifier gain of 12. 5. 35

Current Balance COMPx Pin • A 2 -phase single output configuration is used here as an example 36

Current Balance COMPx Pin • The sensed current is amplified with a ratio of 12. 5 and then is subtracted from COMP. • The subtracted voltage Ve is then compared with the ramp to generate the duty cycle command. • COMP is the same for the two channels. Also, the two ramps are also the same in magnitude although with 180 degree phase shift. • So, i. e. 1 st channel has current , then Ve 1 is decreased, hence the duty cycle of 1 st channel is reduced that will reduce the current in that channel and then bring back to current balance. 37

Current Balance COMPx Pin 1. 2. Ipeak: inductor peak current Vshr: ramp valley voltage RAMP: it is equal to 0. 5 V The currents are balanced because they have the same COMP, Vshr and RAMP Then the tolerance of inductor DCR (Rsns) will be the peak current tolerance. 38

Current Balance COMPx Pin • To parallel modules without optimized phase shift, Single pin is required for current balance. • The TRK 1 pin in the slave chip should be tied to +5 V to disable the error amplifier. • The COMP pins are tied together to force current balancing. • Vshr pins do not have to be connected because Vshr is very accurate between chips. Its tolerance is a few m. Vs. So with the same equation shown above, we can find the paralleled channels are current balanced. 39

Over Current Protection ILIMx and VSHARE Pin (Master): • • • If the over-current condition persists for seven (7) clock cycles the converter shuts down and initiates a hiccup mode restart. In hiccup mode, the TRKx pin is periodically charged and discharged. After seven hiccup cycles, the controller attempts another soft-start cycle to restore normal operation. If the overload condition persists, the controller returns to the hiccup mode. ILIMx Pin(Slave): Tied to GND Over Current Setting By R 1, R 2 on l. LIMx and VSHARE pin 40

Over Current Protection ILIMx and VSHARE Pin: • U 7 shows the over current protection. If COMP voltage is greater than the ILIM voltage, over current occurs. • VOUT, VSHR and the 20 u. A current source from ILIM pin will determine the ILIM voltage • IPEAK is the peak value of the phase current 41

Over Current Protection • How to calculate R 1 and R 2? for 8 -phase CLK scheme for 6 -phase CLK scheme Ilim voltage is also set by R 1 and R 2 42

Over Current Protection • How to calculate R 1 and R 2? We have calculation spreadsheet to help calculate R 1, R 2 Example: for Vin=12 V, with 8 -phase CLK scheme: DCR unit in mohm, Ipeak unit in Amp Ipeak is the phase current With 6 -phase CLK scheme: R 1 and R 2 unit in Kohm 43

Fault Protection Fault Masking Operation • If the TRKx pin voltage is externally limited below the 1. 4 -V threshold, the controller does not respond to an undervoltage fault and the PGOOD output remains low. • The overcurrent protection continues to terminate PWM cycle every time threshold is exceeded, but the hiccup mode is not entered. 44

Peak Current Mode Control Loop Compensation Peak Current Mode Control Transfer Function Type II Compensator is employed to compensate the loop COMP Vo or DIFFO 45

TPS 40140 Loop Compensation Spreadsheet 46

TPS 40140 Component Selection Spreadsheet 47

TPS 40180 New features • • • Single phase operation Stackable to 8 Phases, multiple controllers can occupy any phase e. Trim. TM allow the user to trim the reference voltage in system. Tis will tighten overall output tolerance by trimming out errors caused by resistor divider and other system tolerance. Thermal warning and thermal shutdown Most Features are similar to TPS 40140 24 pin QFN 49

New 4 -Phase TPS 40140 EVM SYMBOL TYP UNIT VIN 12 V VOUT 1. 2 V IOUT 80 A fsw 300 k. Hz CSD 16406 Q 3 CSD 16401 Q 5 50

New 4 -Phase TPS 40140 EVM Schematic 1 51

New 4 -Phase TPS 40140 EVM Schematic 2 52

EVM Performance Load Regulation Efficiency 12 Vin, 1. 2 V/80 A, Efficiency: 90. 4% 53

EVM Performance Bode Plot 12 Vin, 1. 2 V/80 A, Crossover frequency: 54. 58 k. Hz Phase margin: 54. 65 deg, Gain margin: 12. 78 d. B Current Share 54

EVM Performance Output Transient 12 Vin, 1. 2 Vout/ 20 A-80 A Output Ripple 12 Vin, 1. 2 Vout/ 40 A 55

EVM Performance Switching Node 12 Vin, 1. 2 Vout/ 40 A Start up 12 Vin, 1. 2 Vout/ 40 A 56

Input Bulk Capacitor Savings 3 -phase, 12 Vin, 1. 2 V out, 50 A load Input Bulk Capacitance (u. F) Input Voltage Ripple (m. V) * No syn 47 u. F*6 75 With syn 47 u. F*6 47 u. F*5 47 u. F*4 47 u. F*2 20 21 30 52 * The input ripple voltage is measured across the input bulk capacitor 57

Input Bulk Capacitor Savings • From the experiment results, the input bulk capacitance can be reduced • The system power density can be largely improved • The cost can be reduced by saving the 47 u. F/16 V SP capacitors • The input capacitor life time and reliability can be improved due to less ac current • No high slew rate current provided from the input stage will reduce the EMI effect ( the high ac current loop is very small and constrained on the module) 58

Conclusions TPS 40140/TPS 40180 Dual/ Single Phase Stackable Controller Stackable • Makes design flexible and easy to achieve the desired power capability • Efficiency is highly improved compared with noninterleaved multiphase converter • Input bulk capacitor savings • Output ripple reduction • Excellent phase current sharing 59

Nancy_zhang@ti. com 60