Multicycle Processor Design for Dummies By Jonathan Richard

Overview Instruction Set Architecture (ISA) ¡ Multicycle Datapath ¡ Control ¡

ISA ¡ ¡ Instruction Format 16 total instructions 8 total registers I-code capable of ranges from -32 to 31 as opposed to -8 to 7 for 4 bits R opcode rs rt rd blank 4 bits 3 bits I opcode rs rt addr 4 bits 3 bits 6 bits J opcode addr 4 bits 12 bits

ISA LIST Instruction Type sll I AND Opcode Example Meaning 0 sll $s 2, $s 4, 1 $s 2 = $s 4 << 1 R 1 and $s 2, $s 4, $s 3 $s 2 = $s 4 & $s 3 OR R 2 or $s 2, $s 4, $s 3 $s 2 = $s 4 | $s 3 add R 3 add $s 2, $s 4, $s 3 $s 2 = $s 4 + $s 3 subtract R 4 sub $s 2, $s 4, $s 3 $s 2 = $s 4 - $s 3 add immediate I 5 addi $s 2, $s 4, 20 $s 2 = $s 4 + 20 load word I 6 lw $s 2, 20($s 4) $s 2 = Memory[ $s 4 + 20] store word I 7 sw $s 2, 20($s 4) Memory[$s 4 + 20] = $s 2 branch on not equal I 8 bne $s 2, $s 4, 25 if($s 2 != $s 4) go to PC+4+100 branch on equal I 9 beq $s 2, $s 4, 25 if($s 2 ==$s 4) go to PC+4+100 set on less than R 10 slt $s 2, $s 4, $s 3 if($s 4 < $s 3) $s 2 = 1; else $s 2 = 0 set on less than immed I 11 slti $s 2, $s 4, 20 if($s 4<20) $s 2 = 1; else $s 2 = 0 Jump J 12 j 2500 go to 10000 jump register J 13 jr $ra go to $ra jump and link J 14 jal 2500 $ra = PC + 4; go to 10000 HALT H 15 HT stops processor

Multicycle Datapath PC Source IR Write Control PC PC Write M U X Instr Mem lor. D 111 M D R M U X A R E G I R Mem 2 Reg Mem Read Mem Write ALU Src A Reg Write M U X A L U ALU Src B F I L E Reg Dest B R E G M U X ALU M U X R E G 1 0 Sign Ext ALU Ctrl ALU OP

Control PLA 19 “ 0001” 2 1 x 4 Flip Flop Add Mux “ 0000” Rom 2 4 Rom 1

Control FSM 0 1 Decode, Reg Fetch, Branch Addr Fetch, PC Lw/sw 2 3 Read Mem R 6 Lw Comp Addr Jal I 10 B ALU Op 5 Write Reg Write Mem 7 11 Write Reg Jr 9 8 Comp Addr Sw 4 J Write PC 12 ALU Op, PC 13 Co Addr, PC 14 Write Reg

Control PLA when when when when "0000" "0001" "0010" "0011" "0100" "0101" "0110" "0111" "1000" "1001" "1010" "1011" "1100" "1101" "1110" => => => => data_out<= data_out<= data_out<= data_out<= "110000110000101"; --state "0100000001000"; --state "10000000011000"; --state "110000100100000"; --state "0000100000"; --state "000000010100000"; --state "110000000010000"; --state "000110000000"; --state "000001010001"; --state "00000010010000"; --state "110000000011000"; --state "000010000000"; --state "0000010010001"; --state "111000010011100"; --state "001010000000"; --state 0 Then 1 to go to state 1 1 Then lw/sw/R/B/J 2 lw/sw cycle 3 Then lw or sw 3 lw cycle 4 Then state 4 4 lw cycle 5 Then state 0 5 sw cycle 4 Then state 0 6 R cycle 3 Then state 7 7 R cycle 4 Then state 0 8 Be cycle 3 Then state 0 9 J cycle 3 Then state 0 10 I cycle 3 Then state 11 11 I cycle 4 Then state 0 12 Jr cycle 3 Then state 0 13 Jal cycle 3 Then state 14 14 Jal cycle 4 Then state 0 when others => data_out<= "0000000000"; -- start at state 0

Control Output Pins Control Name 16, 15 Reg. Dst 8 IRWrite 14 Reg. Write 7 PCWrite 13 ALU Src A 6 PCWrite. Cond 12 Mem. Read 5, 4 ALU Op 11 Mem. Write 3, 2 ALU Src B 10 Memto. Reg 1, 0 PC Source lor. D 9 Pins Control Name

ALU Control if ( ALUOp = "01" ) then --cycle 3 case IRCode is when "0000" => data_out<= "100"; --sll when "0001" => data_out<= "010"; --And when "0010" => data_out<= "011"; --xor --when "0011" => data_out<= "000"; --add when "0100" => data_out<= "001"; --sub --when "0101" => data_out<= "000"; --when "0110" => data_out<= "000"; --when "0111" => data_out<= "000"; when "1000" => data_out<= "111"; --bne when "1001" => data_out<= "110"; --beq when "1010" => data_out<= "101"; --stl when "1011" => data_out<= "101"; --stli --when "1100" => data_out<= "000"; --when "1101" => data_out<= "000"; --when "1110" => data_out<= "000"; --when "1111" => data_out<= "000"; when others => data_out<= "000"; end case; else data_out<= "000"; end if;

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