MPCSP Synchronization Problems Receiver to Transmitter Serial Clock

MPC–SP Synchronization Problems: Receiver to Transmitter Serial Clock Synchronization 2. 32 bit @ 40 MHz from 2 x 16 bit @ 80 MHz Frames Recovery 1. Options: Using TLK 2501 Transmit Control / Receive Status bits (1, 2) è Using a Frame Bit in the Data Format (2) è TX_EN TX_ER TXD MPC TLK 2501 TRNS Video Conference of October 10, 2001. LINK 1 SP TLK 2501 RCVR RX_DV RX_ER Lev Uvarov PNPI RXD

Frame Bit Option NO room for a Frame bit 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 FR 1 FR 2 Quality BC 1 BC 0 L/R SE VP Video Conference of October 10, 2001. CLCT Pattern # CSC ID CLCT Pattern ID AM 2 Wire Group ID Lev Uvarov PNPI

TLK 2501 Control / Status Option Table 1. Transmit Data Controls TX_EN Low High TX_ER Low High ENCODED 20 -bit DATA (16 -bit TXD) Idle (< K 28. 5, D 5. 6>, < K 28. 5, D 16. 2>) = 0 x. BCC 5, 0 x. BC 50 Carrier extend (K 23. 7, K 23. 7) = 0 x. F 7 F 7 Normal data character (DX. Y) Transmit error propagation (K 30. 7, K 30. 7) = 0 x. FEFE Table 2. Receive Status Signals RECEIVED 20 -BIT DATA (16 -bit RXD) RX_DV/ LOS RX_ER Idle (< K 28. 5, D 5. 6>, < K 28. 5, D 16. 2>) 0 x. BC 50 = 0 x. BCC 5, Low Carrier extend (K 23. 7, K 23. 7) = 0 x. F 7 F 7 Low High Low High Normal data character (DX. Y) Receive error propagation (K 30. 7, K 30. 7) = 0 x. FEFE 2 -bit TLK 2501 Control / Status allows proper synchronization Video Conference of October 10, 2001. 3 Lev Uvarov PNPI

Transmit / Receive Timing GTX_CLK TX_EN TX_ER TXDn BC 3563: FR 0 BC 3563: FR 1 BC 0: FR 2 Figure 1. Transmit Side Timing Diagram RX_CLK RX_DV RX_ER RXDn IDLE BC 0: FR 1 BC 0: FR 2 Figure 2. Receive Side Timing Diagram Video Conference of October 10, 2001. 4 Lev Uvarov PNPI

BX Synchronization TLK 2501 RECEIVERS ALIGNMENT FIFOs ENW WCLK WDATA ENR RCLK RDATA 2 RX_DV RX_CLK RXD ENW WCLK WDATA ENR RCLK RDATA 15 RX_DV RX_CLK RXD ENW WCLK WDATA ENR RCLK RDATA 1 & BC 0 : FR 1 RX_DV RX_CLK RXD DQ CLK RD_CLK Figure 3. Simplified Alignment Schematics. Each channel enables FIFO writes as soon as its RX_DV becomes HIGH (i. e. on bunch crossing Zero, First Frame). The latest channel enables FIFO reads. All FIFOs read BC 0 : FR 1 as a first word. Video Conference of October 10, 2001. 5 Lev Uvarov PNPI