MPC 5748 G Calypso 6 M Cut 2

MPC 5748 G (Calypso 6 M) Cut 2. 0/3. 0 Comparison Summary Version 1 20, July 2016 EXTERNAL USE

Introduction • • The purpose of this presentation is to compare MPC 5748 G cut 3. 0 to MPC 5748 G cut 2. 0 MPC 5748 G Version/Cut Mask ID SIUL 2_MIDR 1 [MAJOR_MASK] JTAG ID 2. 0 1 N 81 M 0 x 1 0 x 0988_101 D 3. 0 0 N 78 S 0 x 2 0 x 0988_201 D Calypso 6 M family part numbers: −MPC 5746 G, 1 EXTERNAL USE MPC 5747 G, MPC 5748 G, MPC 5747 C, MPC 5748 C,

MPC 5748 G errata summary • The following erratum were published in MPC 5748 G cut 2. 0 errata document −Revision 2 (released June 2016) −Find on nxp. com (search “MPC 5748 G_1 N 81 M”) 2 EXTERNAL USE

MPC 5748 G cut 2. 0/3. 0 errata summary Erratum ID Cut 2. 0 1 N 81 M Cut 3. 0 0 N 78 S e 7885 ENET: Potential sequencing issue with TDAR in Multi-Queue mode YES no e 7991 FLASH: Rapid Program or Erase Suspend fail status YES e 8042 FCCU: EOUT signals are active, even when error out signaling is disabled YES no e 8080 LINFlex. D: TX pin gets set to High-Z when in IDLE state YES no e 8180 HSM: e 200 z 0 Nexus interface DQTAG implemented as variable length field in DQM message YES YES no e 8406 e 8714 3 Erratum Description SMPU: Process Identifier region hit determination is not available in debug mode e 10214 STCU & HSM: LBIST on devices with HSM enabled can cause stuck in reset ADC: Conversions on an open channel with the presampling feature enabled do not return the expected results e 8759 Flex. CAN: FD frame format not compliant to the new ISO/CD 11898 -1: 2014 -12 -11 YES no e 8770 Flex. RAY: Missing TX frames on Channel B when in dual channel mode and Channel A is disabled YES e 8868 WKPU: Wakeup Pads pull-ups cannot be enabled in Standby Mode YES no e 8870 NEXUS: Mutli core tracing using NEXUS 3 gives corrupted traces for the case when the cores are in the ratio of 2: 1 YES no e 8871 ME: In STANDBY/LPU STANDBY modes, if FIRC is disabled all 256 k. B of STANDBY RAM is retained YES no e 8880 MEMU: After exit from LPU RUN mode, the MEMU_PROT registers are uninitialized which may impact the usage of MEMU YES no e 8883 HSM: Input Output Control enables pad and alternative pad YES no EXTERNAL USE

MPC 5748 G cut 2. 0/3. 0 errata summary Erratum ID e 8898 e 8901 ME: For a supply voltage of greater than 5. 3 V the MCU may be reset during a LPU_STANDBY to LPU_RUN mode transition Flash: Flash internal regulation mode may lead to power-on-reset when in STANDBY and LPU modes Cut 2. 0 1 N 81 M Cut 3. 0 0 N 78 S YES no e 8902 STM: The STM Counter Register will not report count value when TEN is cleared YES no e 8933 LINFlex. D: Inconsistent sync field may cause an incorrect baud rate and the Sync Field Error Flag may not be set YES e 8938 LINFlex. D: Corruption of Tx data in LIN mode with DMA feature enabled (applicable to LIN 1) YES no e 8939 LINFlex. D: Tx through DMA can be re-triggered after abort in LIN/UART modes or can prematurely end on the event of bit error with LINCR 2[IOBE] bit being set in LIN mode (applicable only for LIN 1) YES no e 9076 FCCU: Fault Collection and Control Unit glitch filter behavior is indeterministic YES no e 9200 MC_ME and LPU: JTAG TCK pin must be configured to ensure successful exit from STANDBY and LPU modes YES no e 9321 ADC: Conversions may fail if Pre-Sampling is enabled YES no YES e 9328 e 9335 e 9873 4 Erratum Description ENET: Not possible to set the entire range of the ENET Timer Compare Capture Register (ENET_TCCR 0[TCC] and ENET_TCCR 1[TCC]) IAHB: Default programming of Intelligent AHB Gasket pending read optimisation can lead to masters stalling or receiving incorrect or spurious data PFLASH: Calibration remap to flash memory not supported on 16 KB and 32 KB flash blocks in address range 0 x 00 F 90000 -0 x 00 FBFFFF e 9978 e. MIOS: Unexpected channel flag assertion during GPIO to MCB mode transition YES e 9995 DSPI 0 and DSPI 1: Frame transfer does not restart in case of DSI parity error in master mode YES no EXTERNAL USE

MPC 5748 G cut 2. 0/3. 0 errata summary Erratum ID Cut 2. 0 1 N 81 M Cut 3. 0 0 N 78 S e 9996 DSPI 0 and DSPI 1: Frame transfer does not restart after DSI frame matches pre-programmed value YES no e 10103 STCU 2: Unexpected STCU self-test timeout can occur when a short functional reset is triggered during execution of online self-test YES e 10118 HSM: TRNG can only select FIRC for clock source YES e 10132 LPU: Mode transition to LPU_STOP or LPU_STANDBY may not complete YES no YES no YES YES no e 10141 e 10143 e 10214 e 10323 e 10361 e 10362 e 10368 e 10440 5 Erratum Description LPU: LPU_RUN mode system clock must be preconfigured for undivided FIRC prior to LPU_STANDBY entry CMP: Analog Comparator 0 (CMP_0) output state is high-impedance during exit from STANDBY mode STCU & HSM: LBIST on devices with HSM enabled can cause stuck in reset MC_ME: The transition from DRUN/RUN mode to STANDBY will not complete if a wake-up is triggered in a 50 n. S window. MC_ME & LPU: The transition between DRUN/RUN mode to STANDBY or DRUN/RUN mode to LPU_RUN may not complete if EXR is asserted. MC_ME & LPU: The transition between DRUN/RUN mode to STANDBY or DRUN/RUN mode to LPU_RUN may not complete if any LVD is asserted or PORST goes low Flex. CAN: Transition of the CAN FD operation enable bit may lead Flex. CAN logic to an inconsistent state. MC_ME & LPU: The transition between DRUN/RUN mode to STANDBY or DRUN/RUN mode to LPU_RUN may not complete if a reset is asserted. EXTERNAL USE

Cut 3. 0 errata fixes additional information Erratum ID Cut 2. 0 1 N 81 M HSM control register: HSM_IOCTL[D 0_EN 0] enables output for both PI[6] & PD[12] HSM_IOCTL[D 0_EN 1] enables output for both PI[7] & PB[12] Cut 3. 0 0 N 78 S Separate control for each output: HSM control register: HSM_IOCTL[D 0_EN 0] enables output of PI[6] HSM_IOCTL[D 0_EN 1] enables output of PI[7] HSM_IOCTL[D 0_EN 2] enables output of PD[12] HSM_IOCTL[D 0_EN 3] enables output of PB[12] e 8883 HSM: Input Output Control enables pad and alternative pad control e 8759 Flex. CAN: FD frame format not compliant to the new ISO/CD 11898 -1: ISO/WD 11898 -1: 2013 -12 -13 2014 -12 -11 ISO/CD 11898 -1: 2014 -12 -11 WKPU: Wakeup Pads pull-ups cannot Pull-down enabled via the be enabled in Standby Mode WKPU_WIPUER Pull-up/down enabled via the WKPU_WIPUER. By default pull-down is selected at SIUL 2_MSCRx[PUS] = 0 (set to 1 for pull -up) e 8868 6 Erratum Description EXTERNAL USE

Cut 3. 0 added functionality Item Module NEW_1 Ethernet NEW_2 Ethernet NEW_3 Ethernet Switch PMC NEW_4 (External Voltage Regulator mode) 7 EXTERNAL USE Description Cut 2. 0 1 N 81 M Statistical counters to behave the same as legacy FEC (Fast Ethernet Controller). Statistical counters (ENET_IEEE_R_FRAME_OK Not supported and ENET_IEEE_R_OCTETS_OK) do not increment when ENET_RCR[BC_REJ]=1 and ENET_RCR[PROM]=0. Pulse stretching for ENET_TCSR[TMODE] = Not supported 4'b 1110 or 4'b 11 X 1. Enhancement to Ethernet switch for VLAN resolution table allows VLAN ID specific Not supported tag removal. Cut 3. 0 0 N 78 S Supported When in external regulation mode the PMC uses a counter to delay the exit from a low power mode to ensure the external power supply is ready and stable. By default the counter delay is 1 m. S. Functionality has been Not supported added so that the counter value can be programmed via a DCF record stored in UTEST Delay counter fixed Supported at 1 m. S flash. This allows the low power mode exit time to be optimised based on the specification of the external power supply. If the external power supply remains enabled through the low power mode the delay can be bypassed.

BAF Version Applicable device: BAF 02. 00. 01 Cut 2. 0 1 N 81 M BAF 02. 08. 00. 01 BAF 02. 09. xx 8 EXTERNAL USE Alpha release for Cut 3. 0 (0 N 78 S) Production release for Cut 3. 0 (0 N 78 S) (Details will be published in later version of this document, after closure of Alpha release validation)

BAF differences Item Functional Change BAF 02. 00. 01 Operation BAF 02. 08. 00. 01 Operation When the following conditions are true, the BAF will not handle the ECC exception and will BAF will handle the ECC exception and will force a destructive reset of the SOC. resume the boot header scan in the next boot header location. Improved handling of multiple ECC BAF_1 errors caused by SSCM in BAF during boot header search. 9 EXTERNAL USE All conditions must be true: i. A multi-bit ECC error is present in one of the memory locations in list A ii. A multi-bit ECC error is present in a valid BAF boot header location iii. The BAF does not find a valid boot header in a location preceding (ii), thereby forcing a read of location (ii). List A: 0 x 0100_0000 - 0 x 0100_001 F 0 x 0104_0000 - 0 x 0104_001 F 0 x 0108_0000 - 0 x 0108_001 F 0 x 010 C_0000 - 0 x 010 C_001 F 0 x 0040_4000 - 0 x 0040_401 F 0 x 00 F 8_C 000 – 0 x 00 F 8_C 01 F

BAF differences Item Functional Change Improved handling of multiple errors BAF_2 caused by HSM in BAF during boot header search BAF_3 10 Improved Handling of BAF Cache Invalidation EXTERNAL USE BAF 02. 00. 01 Operation BAF 02. 08. 00. 01 Operation During BAF operation: - If an error occurs during an HSM access to flash whilst searching for a valid boot header, the error status bit (C 55 FMC_MCR[ERR]) and error address (C 55 FMC_ADR[ADDR]) will be updated appropriately. An HSM CPU exception will be triggered. - If an error also occurs during a BAF access to flash whilst searching for a valid boot header, before the HSM exception handler has cleared the error status, the BAF exception handler will read the error address (C 55 FMC_ADR[ADDR]) associated address location in the Z 4 core Machine with the HSM error, rather than the BAF Check Error Registers (MCAR & MCSR) to error. obtain the address for the BAF error. In this case, the BAF cannot handle the error In this case, the BAF will handle the exception and will force a destructive reset of the SOC. and will resume the boot header scan in the next boot header location. During BAF cache invalidation, if the abort condition is reported, the BAF will not handle condition is reported, the BAF will restart the this. cache invalidation. In this scenario, the cache may not be fully In the case where restarting the cache invalidated & may contain random data that invalidation does not clear the abort appears as a valid cache entry. condition, the BAF watchdog will cause a destructive reset of the SOC.

BAF differences Item Functional Change BAF 02. 00. 01 Operation BAF 02. 08. 00. 01 Operation The detection of un-correctable ECC error for During BAF operation, if an error occurs in the an instruction located in cache is disabled. In Improved Handling of BAF Instructioninstruction cache, the cache controller with BAF_4 case of such an error the cache will return an either correct the error or automatically Cache Errors errant instruction leading to unknown invalidate the cache. behaviour. The MCU will boot without applying the DCF records for the following conditions: BAF stops application boot if the DCF • A multi-bit ECC occurs at the DCF Start The BAF checks for a multi-bit ECC at records are not parsed by SSCM BAF_5 Record in UTEST flash (0 x 0040_0300) 0 x 0040_0300 and if detected the BAF will because of multi-bit ECC at DCF Start during the SSCM scan force a destructive reset of the MCU. Record at 0 x 0040_0300 • The Soft DCF Record Start Address (located at 0 x 0040_00 C 0) is not 0 x 0040_0300 11 EXTERNAL USE

Revision History Revision Changes Approvers V 0 Pre-release of Initial revision (excluding BAF updates) - MPC 5748 G Applications Lead Engineer MPC 5748 G Design Lead Engineer MPC 5748 G Systems & Applications Engineering Manager V 1 Initial release - MPC 5748 G Applications Lead Engineer MPC 5748 G Design Lead Engineer MPC 5748 G Systems & Applications Engineering Manager 12 EXTERNAL USE