Modeling Flash Memories for IC Designs Luca Larcher

Modeling Flash Memories for IC Designs Luca Larcher Università di Modena e Reggio Emilia - Italy luca. larcher@unimore. it Luca Larcher September, the 14 th Università degli Studi di Modena e Reggio Emilia

Flash memories l l Flash memory market increased exponentially in the last years Flash are pervasive in every modern electronic system Luca Larcher September, the 14 th Università degli Studi di Modena e Reggio Emilia

Floating-Gate (FG) transistor n n The FG transistor is the basic element of NOR and NAND Flash memories The information bit is stored by transistor threshold voltage (VT), which can be changed in a non-destructive way by injecting/removing charge to/from FG Luca Larcher September, the 14 th Università degli Studi di Modena e Reggio Emilia

NOR Flash array In a NOR array, a cell, i. e. a FG transistor is identified by a WL – BL cross Single NOR Flash = FG MOSFET Sourcelines G Bitlines (BL) Wordlines (WL) n S D Luca Larcher September, the 14 th Università degli Studi di Modena e Reggio Emilia

NAND Flash array Bitlines n BSL Select Transistors n NAND Flash cells are organized in strings Each string is comprised of 32/64 cells, connected in series High density, i. e. high capacity is thus achieved 16 Wordlines n GSL Luca Larcher September, the 14 th Università degli Studi di Modena e Reggio Emilia

Outline l Motivations l Floating Gate (FG) transistor model: l l DC model and FG voltage calculation l Transient model l Program/erase current l Stress Induced Leakage Current, SILC NOR and NAND Flash Spice-like models l Parameters and extraction procedure l Simulation results l Conclusions Luca Larcher September, the 14 th Università degli Studi di Modena e Reggio Emilia

Motivations l l l Designing NAND and NOR Flash memories requires Spicelike circuit simulations, that need accurate compact models to be effective Flash memory cells are usually replaced with standard MOS in industry circuit simulations FG potential is usually calculated through the capacitive coupling coefficient method, i= Ci/CT Constant capacitive coupling coefficients leads to errors in VFG calculation Optimum models should be: Spice-like, compact, accurate, usable in DC and transient conditions Luca Larcher September, the 14 th Università degli Studi di Modena e Reggio Emilia

The FG transistor DC model CPP = interpoly dielectric capacitance VFG = Floating Gate voltage Luca Larcher September, the 14 th Università degli Studi di Modena e Reggio Emilia

VFG calculation l VFG is calculated by solving the charge neutrality equation at the FG node: QMOS + QCPP = QP/E l l l QCPP = CPP(VFG-VCG) QP/E = charge injected into the FG during program/erase (constant in DC conditions) QMOS = f(VFG, VS, VB, VD) is a the charge on the MOS gate, which is a complex function of voltages, calculated by means of the MOS model charge equations Luca Larcher September, the 14 th Università degli Studi di Modena e Reggio Emilia

Solution of charge equation l The charge neutrality equation is an implicit equation in VFG: F(VFG) = QMOS(VFG) + QCPP(VFG) – QW/E = 0 l l l No analytical solution due to the complex QMOS expression Spice-like simulator solves it numerically through suitable convergence algorithms F is monotonic versus VFG for all bias combinations (VCG, VS, VB, VD), assuring the uniqueness, i. e. the physical meaning of the derived VFG solution Luca Larcher September, the 14 th Università degli Studi di Modena e Reggio Emilia

The FG transistor transient model l Current sources (IW 1, IW 2, IW 3) are included to model program and erase currents, i. e. Fowler-Nordheim (FN) and Channel Hot Electron (CHE) currents Luca Larcher September, the 14 th Università degli Studi di Modena e Reggio Emilia

Fowler-Nordheim current sources l Current sources analytically modeling Fowler/Nordheim currents allow reproducing program-erase and erase operations of NAND and NOR Flash memories, respectively. q AT AFN , BFN q FOX q Luca Larcher September, the 14 th = area of the tunneling region = Fowler-Nordheim physical coefficients depending on the Si/Si. O 2 barrier = electric field across the tunnel oxide Università degli Studi di Modena e Reggio Emilia

FOX calculation VFB = flat-band voltage – S = surface potential drop at Si/Si. O 2 interface – P = surface potential drop at poly-Si/Si. O 2 interface To correctly evaluate S and P, poly depletion and charge quantization effects are taken into account through a self consistent model [1] The so calculated FOX has been included in the FG model through empirical formulas – l l [1] L. Larcher et al. , “A new model of gate capacitance …”, IEEE Trans. Elect. Devices Luca Larcher September, the 14 th Università degli Studi di Modena e Reggio Emilia

CHE current source CHE and Channel Initiated Secondary ELectron (CHISEL) currents can be modeled through simplified approaches allowing modeling the high energy distribution of hot carriers l [2] L. Larcher, P. Pavan, “A New Analytical Model of Channel Hot Electron (CHE) and CHannel Initiated Secondary ELectron (CHISEL) …, ” MSM 2002, pp. 738 -741. Luca Larcher September, the 14 th Università degli Studi di Modena e Reggio Emilia

Stress Induced Leakage Current, SILC [3] is included through current sources allowing simulating the threshold voltage degradation due to the aging of the tunnel oxide induced by P/E cycles SILC modeled assuming the inelastic Phonon Trap-Assisted Tunneling (PTAT) as conduction mechanism l l Si. O 2 cathode Ep [3] L. Larcher et al. , IEEE Trans. Electr. Devices, Vol. 48, N. 2, 2001, pp. 285 -288. Luca Larcher September, the 14 th x. T tox anode Università degli Studi di Modena e Reggio Emilia

NOR Flash model & parameters l l The NOR Flash Spice-like model is the FG MOSFET model Parameters of M 1 are extracted applying the standard MOSFET parameter extraction procedure to the dummy cell, that is a cell with FG and CG short-circuited Additional parameters from SEM measurements and TCAD simulations : FG-CG capacitance; parameters of current sources Practically, no additional costs compared to a standard MOSFET Luca Larcher September, the 14 th Università degli Studi di Modena e Reggio Emilia

NAND Flash model & parameters l The NAND Flash memory string model is a sub-circuit comprised of equivalent dummy cell MOSFETs, inter-poly capacitances, coupling capacitances, P/E current sources Luca Larcher September, the 14 th Università degli Studi di Modena e Reggio Emilia

NAND Flash model & parameters -2 l l l Coupling capacitances between FGs of adjacent cells, FCF and CFFB, are additional parameters derived from SEM measurements and TCAD simulations Parameter of the equivalent MOSFET are extracted from a string of dummy cells, paying attention to correctly account for series resistance effects Again, current sources can be inserted to account for program/erase Fowler-Nordheim currents Luca Larcher September, the 14 th Università degli Studi di Modena e Reggio Emilia

DC – NOR Flash: IDS-VCG W=0. 25 mm L=0. 375 mm Luca Larcher September, the 14 th Università degli Studi di Modena e Reggio Emilia

DC – NOR Flash: IDS-VDS Luca Larcher September, the 14 th Università degli Studi di Modena e Reggio Emilia

DC – NOR Flash: IDS-VCG W=0. 16 mm L=0. 3 mm Luca Larcher September, the 14 th Università degli Studi di Modena e Reggio Emilia

DC - NAND Flash: IDS-VCG Luca Larcher September, the 14 th Università degli Studi di Modena e Reggio Emilia

Erase – NOR Flash: VT - time Erase bias: D float VS=VB=8 V Luca Larcher September, the 14 th Università degli Studi di Modena e Reggio Emilia

Erase – NOR Flash: VT - time Luca Larcher September, the 14 th Università degli Studi di Modena e Reggio Emilia

Program – E 2 PROM Flash: VT 4 3 Lines: simulations Symbols: measures VT (V) 2 1 0. 3 0 0. 4 0. 5 TRISE(m s) -1 0. 6 12 V VCG-ramp VD=VB=0 V TRISE VS=0 V -2 -3 No free parameter to improve the fitting quality!! 0 0. 1 0. 2 0. 3 0. 4 0. 5 0. 6 0. 7 0. 8 0. 9 1 Time (ms) Luca Larcher September, the 14 th Università degli Studi di Modena e Reggio Emilia

Program – E 2 PROM Flash: tunnel current 60 ITUN (p. A) excellent fitting using real VCG 50 ramp!! VVCG ramp D-ramp Nominal 40 TRISE 30 Real 20 10 0 0. 4 Lines: simulations Symbols: measures 0. 5 0. 6 0. 7 0. 8 0. 9 1. 0 1. 1 Time (ms) Luca Larcher September, the 14 th Università degli Studi di Modena e Reggio Emilia

E 2 PROM Flash: retention simulation NC = number of P/E cycles E 2 PROM cell left unbiased in retention VT reduction induced by SILC, included by some current sources Luca Larcher September, the 14 th Università degli Studi di Modena e Reggio Emilia

Advantages & conclusions q This Flash memory modeling approach has several advantages q The parameter extraction procedure is simple it is similar to the one of a standard MOSFET and few additional parameters are derived from SEM measurements and TCAD simulations q The simulation time is comparable to MOSFET q VFG calculation procedure does NOT use capacitive coupling coefficients the VFG calculation is much more accurate compared to the usual method considering capacitive coupling coefficients as constants, which introduces errors Luca Larcher September, the 14 th Università degli Studi di Modena e Reggio Emilia

Flash coupling coefficients: CG Luca Larcher September, the 14 th Università degli Studi di Modena e Reggio Emilia

Advantages & conclusions -2 q NOR and NAND Flash compact models are simply developed as sub-circuit q DC, transient and reliability simulations of single devices and circuits excellently reproduce measurements without free parameters to improve the fitting quality q Easily scalable: scaling rules are taken into account in the MOSFET model itself, and they do not affect the VFG calculation q Easily upgradeable: voltage and current sources can be replaced/modified independently q Can be used for statistical analysis (effects of statistical fluctuation of critical parameters, …) Luca Larcher September, the 14 th Università degli Studi di Modena e Reggio Emilia

References o n n n Paolo Pavan, Luca Larcher, Andrea Marmiroli, Floating Gate devices: Operation and Compact Modeling, Kluwer Academic Publishers, 2004, 140 pp. , ISBN 1 -40207731 -9 L. Larcher et al. , Bias and W/L Dependence of Capacitive Coupling Coefficients in Floating Gate Memory Cells, IEEE Trans. on Electron Devices, Vol. 48(9), pp. 2081 -2089, 2001. L. Larcher et al. , A New Compact DC Model of Floating Gate Memory Cells Without Capacitive Coupling Coefficients, IEEE Trans. on Electron Devices, Vol. 49(2), pp. 301 -307, 2002. L. Larcher et al. , A complete model of E 2 PROM memory cells for circuit simulations, IEEE Trans. on CAD, Vol. 22(8), pp. 1072 -1079, 2003. L. Larcher and P. Pavan, Statistical simulations for Flash memory reliability analysis and prediction, IEEE Trans. on Electron Device, Vol. 51(10), pp. 16361643, 2004. Luca Larcher et al. , Modeling NAND Flash memories for circuit simulations, IEEE SISPAD, 2007 L. Larcher et al. , Flash memories for So. C: an overview on system constraints and technology issues, (invited paper) IEEE IWSo. C 2005, 2005. Luca Larcher September, the 14 th Università degli Studi di Modena e Reggio Emilia