MIPS Coding Continued Complete MIPS code data save

MIPS Coding Continued

Complete MIPS code. data save: . word 10, 10, 10, 11, 12, . text. globl main: li $s 3, 0 li $s 5, 10 la $s 6, save Loop: sll $t 1, $s 3, 2 add $t 1, $s 6 lw $t 0, 0($t 1) bne $t 0, $s 5, Exit addi $s 3, 1 j Loop Exit: done: li $v 0, 10 # these two lines are to tell the simulator to stop syscall

Complete MIPS code • It has a data segment and a code (text) segment. • The beginning of the data segment in the assembly source code is indicated as. data and followed by several declarations such as – A: . word 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 meaning an array of words whose starting address is associated with label ``A. ’’

Complete MIPS code • The text segment in the source code usually starts with. text. globl main: where ``main’’ is the label associated with the address of the first instruction of the code. • And the code usually ends with li $v 0, 10 # telling the simulator to stop syscall • Comment with `#’

Exercise 1 • Suppose we have three arrays, A, B, C, all of size 10. Now we want to set C[i] = min(A[i], B[i]) for all 0<= i <= 9. 6/14/2021 week 04 -3. ppt 5

Exercise 1 • Suppose we have three arrays, A, B, C, all of size 10. Now we want to set C[i] = min(A[i], B[i]) for all 0<= i <= 9. • First, we need a loop to walk through the elements (done before) • Second, we need to be able to read the elements (done before) • Third, we need to be able to compare two numbers (done before) • Fourth, we need to write back to the memory (easy) 6/14/2021 week 04 -3. ppt 6

. data A: B: C: . word 12, 34, 67, 1, 45, 90, 11, 33, 67, 19. word 90, 2, 93, 66, 8, 120, 121, 11, 33, 9. word 0, 0, 0, 0 . text. globl main: la $s 0, A la $s 1, B la $s 2, C li $s 3, 10 li $t 0, 0 LOOP: sll $t 4, $t 0, 2 add $t 5, $t 4, $s 0 lw $t 1, 0($t 5) add $t 6, $t 4, $s 1 lw $t 2, 0($t 6) slt $t 5, $t 1, $t 2 beq $t 5, $0, L 1 ori $t 8, $t 1, 0 j L 2 L 1: ori $t 8, $t 2, 0 L 2: add $t 6, $t 4, $s 2 sw $t 8, 0($t 6) addi $t 0, 1 bne $t 0, $s 3, LOOP done: li $v 0, 10 syscall # using $t 0 as i # # # # # $t 4 = i * 4 $t 5 will have the address of A[i] $t 1 has A[i] $t 6 will have the address of B[i] $t 2 has B[i] set $t 5 to be 1 if A[i] < B[i] if $t 5 == 0, goto L 1. in this case, A[i] >= B[i] setting $t 8 to be A[i] always remember to jump in an if else! # setting $t 8 to be B[i] # # now $t 6 has the address of C[i] now C[i] has the minimum of A[i] and B[i] i ++ go back if not yet 10 times

SPIM • Run codes with SPIM is a simulator. – Use any editor to write the source file, save it as an. asm file. – Run PCSpim, load the source file. – F 10 to step through the code. Monitor how the registers change. – F 5 to run the code – Can set breakpoints for debugging • SPIM can be downloaded at http: //pages. cs. wisc. edu/~larus/spim. html • Lots of good references online, like https: //www. cs. tcd. ie/~waldroj/itral/spim_ref. html

Representing Instructions in Computers • Note that computers only have 0’s and 1’s • Before we can load MIPS instructions into memory, they need to be translated into machine instructions, which consist of only 0’s and 1’s – In other words, we need to encode or represent instructions – The symbolic representation of machine instructions is called assembly language – The binary representation of instructions is called machine language • A sequence of instructions in binary form is called machine code 6/14/2021 CDA 3100 9

Example 6/14/2021 CDA 3100 10

MIPS Instruction Encoding • Each MIPS instruction is exactly 32 bits – R-type (register type) – I-type (immediate type) – J-type (jump type) op rs rt rd op rs rt 16 bit address or constant op 6/14/2021 shamt funct 26 bit address CDA 3100 11

R-Type Encoding 31 26 25 opcode 21 20 rs 16 15 rt 11 10 rd 6 5 shamt 0 funct rd rt add $4, $3, $2 rs 31 26 25 21 20 16 15 11 10 6 5 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 opcode rs rt rd shamt funct 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 Encoding = 0 x 00622020 6/14/2021 CDA 3100 12

I-type Encoding 31 26 25 opcode 21 20 rs 16 15 0 rt Immediate Value rt Immediate lw $5, 3000($2) rs 31 26 25 21 20 16 15 0 1 0 0 0 1 0 1 1 1 0 0 0 opcode rs rt Immediate Value 1 0 0 0 1 0 0 1 0 1 1 1 0 0 0 Encoding = 0 x 8 C 450 BB 8 6/14/2021 CDA 3100 13

I-type Encoding 31 26 25 opcode 21 20 rs 16 15 0 rt Immediate Value rt Immediate sw $5, 3000($2) rs 31 26 25 opcode 16 15 21 20 rs rt 0 Immediate Value Encoding = 6/14/2021 CDA 3100 14

I-type Encoding 31 26 25 opcode 21 20 rs 16 15 0 rt Immediate Value rt Immediate sw $5, 3000($2) rs 31 26 25 21 20 16 15 0 1 0 1 1 0 0 0 0 1 1 1 0 0 0 opcode rs rt Immediate Value 1 0 1 1 0 0 0 0 1 1 1 0 0 0 Encoding = 0 x. AC 450 BB 8 6/14/2021 CDA 3100 15

I-type Encoding 31 26 25 opcode 21 20 rs 16 15 0 rt Immediate Value rt Immediate addi $s 0, 95 rs 31 26 25 opcode 16 15 21 20 rs rt 0 Immediate Value Encoding = 6/14/2021 CDA 3100 16

I-type Encoding 31 26 25 opcode 21 20 rs 16 15 0 rt Immediate Value rt Immediate addi $s 0, 95 rs 31 26 25 21 20 16 15 0 0 0 1 0 0 0 01 0 0 0 0 1 1 1 opcode rs rt Immediate Value 0 0 1 0 0 0 0 0 0 0 1 1 1 Encoding = 0 x 2210005 F 6/14/2021 CDA 3100 17

J-type Encoding 31 26 25 0 opcode Jump Address j 0 x 0040007 c: the address of the instruction to jump to. When encoding it, take the bit 2 to bit 27. 31 26 25 0 0 0 1 0 0 0 j 0 x 0040007 c 0 0 0 1 0 0 0 0 1 1 1 opcode Jump Address 0 0 0 0 1 0 0 0 0 0 1 1 1 Encoding = 0 x 0810001 F

How to Encode Branch Instructions • To encode these branch instructions, we first need to figure out the value for the associated label – This will be done by the assembler – Note that the MIPS has the alignment restriction, which means all the labels will be a multiple of 4 – To increase the range, the address divided by 4 is actually encoded • In other words, the address is in terms of words (32 bits), rather than bytes 6/14/2021 week 04 -3. ppt 19

Encoding Conditional Branch Instructions • It branches the number of the instructions specified by the offset if register rs equals to register rt – In the stored-program concept, we implicitly need a register to hold the address of the current instruction being executed • Which is called program counter (PC) (should be called instruction address register) – What is the value of PC after we finish executing the current instruction? 6/14/2021 week 04 -3. ppt 20

Encoding Conditional Branch Instructions • PC-relative addressing – The offset of conditional branch instructions is relative to PC + 4 – Since all MIPS instructions are 4 bytes long, the offset refers to the number of words to the next instruction instead of the number of bytes 6/14/2021 week 04 -3. ppt 21

Encoding bne 31 26 25 opcode 21 20 rs 16 15 0 rt Immediate Value rs Label/Offset bne $19, $20, Else rt 31 26 25 21 20 16 15 0 0 1 0 1 1 0 0 1 1 1 0 0 0 0 0 1 0 opcode rs rt Immediate Value 0 0 0 1 1 1 0 0 0 0 0 1 0 Encoding = 0 x 16740002 6/14/2021 week 04 -3. ppt 22