MIPS Assembly Tutorial Types of Instructions There are

MIPS Assembly Tutorial

Types of Instructions • There are 3 main types of assembly instructions – Arithmetic - add, sub, mul, shifts, and, or, etc. – Load/store – Conditional - branches

Arithmetic Instructions add a, b, c add a, a, d add a, a, e a = b+c a = d+b+c a = e+d+b+c Example: Translate the following instructions to assembly code a = b+c d = a-e Solution: add a, b, c sub d, a, e

Arithmetic Instructions Example: Translate the following instructions to assembly code. Remember with RISC, only 1 operation per instruction! HINT - you may need temporary variables f = (g+h) - (i+j) Solution: add t 0, g, h add t 1, i, j sub f, t 0, t 1

Operands • In assembly code, you can’t use variables such as a, b, c, etc • In RISC instruction sets, operands must be registers such as r 1, r 2, r 3, etc – r 0 is typically reserved to hold the immediate value of 0 – There is a limited number of registers • MIPS has 32

Arithmetic Instructions Using Registers Example: Translate the following instructions to assembly code. Assume that g, h, i, and j are already stored in r 1, r 2, r 3, and r 4. Store f in r 5 f = (g+h) - (i+j) Solution: add r 6, r 1, r 2 add r 7, r 3, r 4 sub r 5, r 6, r 7

What about more data? ? • With only a limited number of registers, not all data can be stored in registers at the same time. – Registers only store data that is currently being operated on • Variables are stored in memory and then loaded into registers when needed using data transfer instructions – Load word (lw) and store word (sw)

Load and store word • Load word format – lw destination register, memory location • Store word format – sw source register, memory location • Memory location format – Offset(base address) • Base address = starting location of data in memory • Offset = how far away is location to access from base address – Values are added together

LW Example: Assume that A is an array of 100 words. Assume the base address is stored in r 3, g is in r 1 and h is in r 2 g = h + A[8] Solution: Offset lw r 4, 8(r 3) add r 1, r 2, r 4 Base Address This is simplified, more details later…

Data in Memory • All variables/data are stored in memory – You will need to do this in your assembler – Your ISS will need a data structure to hold main memory • Array is fine

Addressing Data • Architecture usually addresses data in bytes (byte addressable) – 32 -bit architecture = 4 bytes = 1 word • lw/sw load/store 1 word or 4 bytes – Thus, data/inst addresses are multiples of 4 • Data is word aligned to be more efficient

Data in Memory. . . 12 8 4 0 10 101 1 Address Data

LW/SW Example: Assume that A is an array of 100 words. Assume the base address is stored in r 3 and h is stored in r 2. You may directly calculate the offset. Remember, each data piece is 4 bytes when calculating the offset A[12] = h+A[8] Solution: lw r 1, 32(r 3) add r 4, r 2, r 1 sw r 4, 48(r 3)

LW/SW Example: Assume that A is an array of 100 words. Assume the base address is stored in r 3 and g, h, and i are in r 1, r 2, and r 4 respectively. Calculate the offset using assembly instructions but don’t use multiplication yet (mult instruction is different) g = h + A[i] Solution: add r 5, r 4 add r 5, r 5 add r 5, r 3 lw r 6, 0(r 5) add r 1, r 6, r 2 # Temp reg r 5=2*i # Temp reg r 5=4*i # t 1 = addr of A[i] (4*i+r 3) # Temp reg r 0=a[i] # g=h+a[i]

Translating MIPS Assm Language to Machine Language • Translate human readable assembly code to machine readable code (binary) – I will show examples in decimal for readability – This is what you assembler will do but it will output in binary.

MIPS -> Machine Language Example: Show the real MIPS language version of the following instruction in both decimal and binary add r 0, r 1, r 2 Solution: decimal 0 0 1 2 0 32 00010 00000 100000 5 bits 6 bits binary 0000001 6 bits 5 bits Each segment is referred to as a field. Details to come….

MIPS Fields • MIPS fields are giving names to make them easier to discuss op rs rt 6 bits 5 bits rd 5 bits shamt funct 5 bits 6 bits • op: Basic operation of the instruction, typically called the opcode • rs: The first register source operand • rt: The second register source operand • rd: The register destination operand, it gets the result of the operation • shamt: Shift amount (0 if not shift instruction) • funct: Function. This field selects the specific variant of the operation in the op field, and is sometimes called the function code

MIPS Fields • Problem occurs with an instruction needs a longer field than that showed on the previous slide – I. e. LW must specify 2 registers and a constant. Limited to 5 -bit constant if use previous format. • Solution: There are different formats for different types of instructions – Previous slide is R-type (R-format): • R=register

MIPS Fields op rs rt 6 bits 5 bits address 16 bits • I-type (I-format) – I=immediate – Now LW can specify an address up to 16 bits • Opcode determines the format

MIPS Instruction Encoding

MIPS Asm -> Machine Language Example: Assume r 1 is the base of A and r 2 corresponds to h, the C statement: A[300] = h + A[300] is compiled to: lw r 0, 1200(r 1) add r 0, r 2, r 0 sw r 0, 1200(r 1) What is the MIPS machine code for these three instructions? (Use figure 3. 5)

MIPS Asm -> Machine lw r 0, 1200(r 1) add r 0, r 2, r 0 Language sw r 0, 1200(r 1) Solution: decimal op rs rt 35 0 1 0 0 2 43 0 1 rd Address /shamt funct 1200 0 0 32 1200 binary 100011 000001 000000 00010 101011 000001 0000 0100 1011 00000 0100 1011 0000 32

Decision Instructions • Branch/jump instructions – Conditional branches • beq register 1, register 2, Label • bne register 1, register 2, Label – Unconditional branches • j Label

Decision Instructions Example: Assume f->r 0, g->r 1, h->r 2, i->r 3, j->r 4 L 1: if ( i==j ) goto L 1 f = g+h f = f-i Solution: L 1: beq r 3, r 4, L 1 add r 0, r 1, r 2 sub r 0, r 3 Labels will need to be translated to instruction address in your assembler

Decision Instructions Example: Assume f->r 0, g->r 1, h->r 2, i->r 3, j->r 4 L 1: if ( i==j ) f = g+h else f = g-h L 2: Solution: L 1: L 2: bne r 3, r 4, L 1 add r 0, r 1, r 2 j L 2 sub r 0, r 1, r 2

Decision Instructions Example: A is 100 elements with the base address in r 5. g->r 1, h->r 2, i->r 3, j->r 4 Loop: g = g+A[i] i = i+j if ( i!=h ) goto Loop Solution: Loop: add r 6, r 3 add r 6, r 6 add r 6, r 5 lw r 7, 0(r 6) add r 1, r 7 add r 3, r 4 bne r 3, r 2, Loop

While Loop • Goto statements are bad, just used them as an example. • You will want to use while loops – Or for loops but I am just showing you while loops

While Loop Example: Base address of save is in r 6. i->r 3, j->r 4, k->r 5 while ( save[i] == k ) i = i+j Solution: Loop: Exit: add r 1, r 3, r 4 add r 1, r 1 add r 1, r 6 lw r 0, 0(r 1) bne r 0, r 5, Exit add r 3, r 4 j Loop

Other Styles of MIPS Addressing • Constant or immediate operands – Programs often use constant values – I. e. incrementing to the next data element while scanning an array • addi instruction - adds an immediate value to a register

Immediate Operands Example: What is the machine code for the following? (Remember the I-format instruction) addi r 4, 4 Solution: decimal op 8 rs 4 rt 4 Immediate 4 binary 001000 00100 0000 0100

Addressing in Branches and Jumps • Last instruction format - J-type (Jformat) opcode Target address • Branches do not use J-type. – Must specify 2 registers to compare – Use I-type