MIPS Arithmetic and Logic Instructions COE 301 Computer
- Slides: 28
MIPS Arithmetic and Logic Instructions COE 301 Computer Organization ICS 233 Computer Architecture and Assembly Language Dr. Marwan Abu-Amara College of Computer Sciences and Engineering King Fahd University of Petroleum and Minerals [Adapted from slides of Dr. M. Mudawar and Dr. A. El-Maleh, KFUPM]
Outline v R-Type Arithmetic, Logical, and Shift Instructions v I-Type Format and Immediate Constants v Pseudo Instructions v Multiplication and Division Instructions Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar slide 2
Instruction Formats v All instructions are 32 -bit wide. Three instruction formats: v Register (R-Type) ² Register-to-register instructions ² Op: operation code specifies the format of the instruction Op 6 Rs 5 Rt 5 Rd 5 sa 5 v Immediate (I-Type) ² 16 -bit immediate constant is part in the instruction Op 6 Rs 5 Rt 5 immediate 16 v Jump (J-Type) ² Used by jump instructions Op 6 Instruction Set Architecture immediate 26 COE 301 – Computer Organization – KFUPM © Muhamed Mudawar slide 3 funct 6
R-Type Format Op 6 Rs 5 Rt 5 Rd 5 sa 5 funct 6 v Op: operation code (opcode) ² Specifies the operation of the instruction ² Also specifies the format of the instruction v funct: function code – extends the opcode ² Up to 26 = 64 functions can be defined for the same opcode ² MIPS uses opcode 0 to define R-type instructions v Three Register Operands (common to many instructions) ² Rs, Rt: first and second source operands ² Rd: destination operand ² sa: the shift amount used by shift instructions Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar slide 4
Integer Add /Subtract Instructions Instruction addu subu $s 1, $s 2, $s 3 Meaning $s 1 = $s 2 + $s 3 $s 1 = $s 2 – $s 3 R-Type Format op = 0 rs = $s 2 rt = $s 3 rd = $s 1 sa = 0 f = 0 x 20 f = 0 x 21 f = 0 x 22 f = 0 x 23 v add & sub: overflow causes an arithmetic exception ² In case of overflow, result is not written to destination register v addu & subu: same operation as add & sub ² However, Overflow is ignored v Many programming languages ignore overflow ² The + operator is translated into addu ² The – operator is translated into subu Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar slide 5
Range, Carry, Borrow, and Overflow v Bits have NO meaning. The same n bits stored in a register can represent an unsigned or a signed integer. v Unsigned Integers: n-bit representation Numbers < 0 Numbers > max Borrow = 1 Subtraction Carry = 1 Addition Finite Set of Unsigned Integers max = 2 n– 1 min = 0 v Signed Integers: n-bit 2's complement representation Numbers < min Numbers > max Negative Overflow min = -2 n-1 Instruction Set Architecture Positive Overflow Finite Set of Signed Integers 0 COE 301 – Computer Organization – KFUPM max = 2 n-1– 1 © Muhamed Mudawar slide 6
Carry and Overflow v Carry is useful when adding (subtracting) unsigned integers ² Carry indicates that the unsigned sum is out of range v Overflow is useful when adding (subtracting) signed integers ² Overflow indicates that the signed sum is out of range v Range for 32 -bit unsigned integers = 0 to (232 – 1) v Range for 32 -bit signed integers = -231 to (231 – 1) v Example 1: Carry = 1, Overflow = 0 (NO overflow) 11111 1 1 1000 0100 0000 1110 0001 0100 0001 + 1111 0000 1111 0101 0010 0000 1000 0011 0000 0001 1101 0110 0001 Unsigned sum is out-of-range, but the Signed sum is correct Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar slide 7
More Examples of Carry and Overflow v Example 2: Carry = 0, Overflow = 1 01111 1 0010 0100 0000 0100 1011 0001 0100 + 0111 1111 0000 0011 0101 0000 0010 1010 0011 0100 1110 0100 0110 Unsigned sum is correct, but the Signed sum is out-of-range v Example 3: Carry = 1, Overflow = 1 1 11 1 1000 0100 0000 0100 1011 0001 0100 + 1001 1111 0000 0011 0101 0000 0010 0011 0100 1110 0100 0110 Both the Unsigned and Signed sums are out-of-range Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar slide 8
Addition/Subtraction Example v Consider the translation of: f = (g+h) – (i+j) v Compiler allocates registers to variables ² Assume that f, g, h, i, and j are allocated registers $s 0 thru $s 4 ² Called the saved registers: $s 0 = $16, $s 1 = $17, …, $s 7 = $23 v Translation of: f = (g+h) – (i+j) addu $t 0, $s 1, $s 2 addu $t 1, $s 3, $s 4 subu $s 0, $t 1 # $t 0 = g + h # $t 1 = i + j # f = (g+h)–(i+j) ² Temporary results are stored in $t 0 = $8 and $t 1 = $9 v Translate: addu $t 0, $s 1, $s 2 to binary code op v Solution: Instruction Set Architecture rs = $s 1 rt = $s 2 rd = $t 0 sa func 000000 10001 10010 01000 00000 100001 COE 301 – Computer Organization – KFUPM © Muhamed Mudawar slide 9
Logical Bitwise Operations v Logical bitwise operations: and, or, xor, nor x y x and y x y 0 0 1 1 0 1 0 0 0 1 0 1 x or y 0 1 1 1 x y x xor y x nor y 0 0 1 1 0 1 0 1 1 0 0 1 v AND instruction is used to clear bits: x and 0 = 0 v OR instruction is used to set bits: x or 1 = 1 v XOR instruction is used to toggle bits: x xor 1 = not x v NOR instruction can be used as a NOT, how? ² nor $s 1, $s 2 is equivalent to not $s 1, $s 2 Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar slide 10 1 0 0 0
Logical Bitwise Instructions Instruction and or xor nor $s 1, $s 2, $s 3 Meaning $s 1 = $s 2 & $s 3 $s 1 = $s 2 | $s 3 $s 1 = $s 2 ^ $s 3 $s 1 = ~($s 2|$s 3) R-Type Format op = 0 rs = $s 2 rt = $s 3 rd = $s 1 sa = 0 f = 0 x 24 f = 0 x 25 f = 0 x 26 f = 0 x 27 v Examples: Assume $s 1 = 0 xabcd 1234 and $s 2 = 0 xffff 0000 and $s 0, $s 1, $s 2 # $s 0 = 0 xabcd 0000 or $s 0, $s 1, $s 2 # $s 0 = 0 xffff 1234 xor $s 0, $s 1, $s 2 # $s 0 = 0 x 54321234 nor $s 0, $s 1, $s 2 # $s 0 = 0 x 0000 edcb Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar slide 11
Shift Operations v Shifting is to move the 32 bits in a register left or right v Shifts by a constant amount: sll, sra ² sll means shift left logical (insert zero from the right) ² srl means shift right logical (insert zero from the left) ² sra means shift right arithmetic (insert sign-bit) ² The 5 -bit shift amount field is used by these instructions sll shift-out MSB srl shift-in 0 sra shift-in sign-bit Instruction Set Architecture 32 -bit register . . . shift-in 0 . . . shift-out LSB COE 301 – Computer Organization – KFUPM © Muhamed Mudawar slide 12
Shift Instructions Instruction sll sra sllv srav $s 1, $s 2, 10 $s 1, $s 2, $s 3 Meaning $s 1 = $s 2 << 10 $s 1 = $s 2>>>10 $s 1 = $s 2 >> 10 $s 1 = $s 2 << $s 3 $s 1 = $s 2>>>$s 3 $s 1 = $s 2 >> $s 3 R-Type Format op = 0 op = 0 rs = 0 rt = $s 2 rs = $s 3 rt = $s 2 rd = $s 1 rd = $s 1 sa = 10 sa = 0 f=2 f=3 f=4 f=6 f=7 v Shifts by a variable amount: sllv, srav ² Same as sll, sra, but a register is used for shift amount ² Only the lower 5 bits of the register are used as the shift amount v Examples: assume that $s 2 = 0 xabcd 1234, $s 3 = 16 sll $s 1, $s 2, 8 $s 1 = $s 2<<8 $s 1 = 0 xcd 123400 sra $s 1, $s 2, 4 $s 1 = $s 2>>4 $s 1 = 0 xfabcd 123 $s 1 = $s 2>>>$s 3 $s 1 = 0 x 0000 abcd srlv $s 1, $s 2, $s 3 op=000000 rs=$s 3=10011 rt=$s 2=10010 rd=$s 1=10001 sa=00000 f=000110 Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar slide 13
Binary Multiplication v Shift-left (sll) instruction can perform multiplication ² When the multiplier is a power of 2 v You can factor any binary number into powers of 2 ² Example: multiply $s 1 by 36 § Factor 36 into (4 + 32) and use distributive property of multiplication ² $s 2 = $s 1*36 = $s 1*(4 + 32) = $s 1*4 + $s 1*32 sll $t 0, $s 1, 2 ; $t 0 = $s 1 * 4 sll $t 1, $s 1, 5 ; $t 1 = $s 1 * 32 addu $s 2, $t 0, $t 1 Instruction Set Architecture COE 301 – Computer Organization – KFUPM ; $s 2 = $s 1 * 36 © Muhamed Mudawar slide 14
Your Turn. . . Multiply $s 1 by 26, using shift and add instructions Hint: 26 = 2 + 8 + 16 sll addu $t 0, $t 1, $s 2, $t 0, $s 2, $s 1, $t 0, $s 1, $s 2, 1 ; $t 0 = $s 1 * 2 3 ; $t 1 = $s 1 * 8 $t 1 ; $s 2 = $s 1 * 10 4 ; $t 0 = $s 1 * 16 $t 0 ; $s 2 = $s 1 * 26 Multiply $s 1 by 31, Hint: 31 = 32 – 1 sll subu $s 2, $s 1, 5 ; $s 2 = $s 1 * 32 $s 2, $s 1 ; $s 2 = $s 1 * 31 Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar slide 15
Outline v R-Type Arithmetic, Logical, and Shift Instructions v I-Type Format and Immediate Constants v Pseudo Instructions v Multiplication and Division Instructions Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar slide 16
I-Type Format v Constants are used quite frequently in programs ² The R-type shift instructions have a 5 -bit shift amount constant ² What about other instructions that need a constant? v I-Type: Instructions with Immediate Operands Op 6 Rs 5 Rt 5 immediate 16 v 16 -bit immediate constant is stored inside the instruction ² Rs is the source register number ² Rt is now the destination register number (for R-type it was Rd) v Examples of I-Type ALU instructions: ² Add immediate: addi $s 1, $s 2, 5 # $s 1 = $s 2 + 5 ² OR immediate: # $s 1 = $s 2 | 5 Instruction Set Architecture ori $s 1, $s 2, 5 COE 301 – Computer Organization – KFUPM © Muhamed Mudawar slide 17
I-Type ALU Instructions Instruction addiu andi ori xori lui $s 1, $s 2, 10 $s 1, $s 2, 10 $s 1, 10 Meaning $s 1 = $s 2 + 10 $s 1 = $s 2 & 10 $s 1 = $s 2 | 10 $s 1 = $s 2 ^ 10 $s 1 = 10 << 16 I-Type Format op = 0 x 8 op = 0 x 9 op = 0 xc op = 0 xd op = 0 xe op = 0 xf rs = $s 2 rs = $s 2 0 rt = $s 1 rt = $s 1 imm 16 = 10 imm 16 = 10 v addi: overflow causes an arithmetic exception ² In case of overflow, result is not written to destination register v addiu: same operation as addi but overflow is ignored v Immediate constant for addi and addiu is signed ² No need for subiu instructions v Immediate constant for andi, ori, xori is unsigned Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar slide 18
Examples: I-Type ALU Instructions v Examples: assume A, B, C are allocated $s 0, $s 1, $s 2 A = B+5; translated as addiu $s 0, $s 1, 5 C = B– 1; translated as addiu $s 2, $s 1, -1 op=001001 rs=$s 1=10001 rt=$s 2=10010 imm = -1 = 11111111 A = B&0 xf; translated andi C as = B|0 xf; translated ori C as = 5; translated as ori A = B; translated as ori $s 0, $s 1, 0 xf $s 2, $zero, 5 $s 0, $s 1, 0 v No need for subi, because addi has signed immediate v Register 0 ($zero) has always the value 0 Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar slide 19
32 -bit Constants v I-Type instructions can have only 16 -bit constants Op 6 Rs 5 Rt 5 immediate 16 v What if we want to load a 32 -bit constant into a register? v Can’t have a 32 -bit constant in I-Type instructions ² We have already fixed the sizes of all instructions to 32 bits v Solution: use two instructions instead of one ² Suppose we want: $s 1=0 x. AC 5165 D 9 (32 -bit constant) ² lui: load upper immediate load upper 16 bits clear lower 16 bits lui $s 1, 0 x. AC 51 $s 1=$17 0 x. AC 51 0 x 0000 ori $s 1, 0 x 65 D 9 $s 1=$17 0 x. AC 51 0 x 65 D 9 Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar slide 20
Outline v R-Type Arithmetic, Logical, and Shift Instructions v I-Type Format and Immediate Constants v Pseudo Instructions v Multiplication and Division Instructions Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar slide 21
Pseudo-Instructions v Introduced by assembler as if they were real instructions ² To facilitate assembly language programming Pseudo-Instructions move $s 1, $s 2 not $s 1, $s 2 li $s 1, -5 li $s 1, 0 xabcd 1234 neg $s 1, $s 2 Conversion to Real Instructions addu $s 1, $zero, $s 2 nor $s 1, $s 2, $zero addiu $s 1, $zero, -5 lui $at, 0 xabcd ori $s 1, $at, 0 x 1234 sub $s 1, $zero, $s 2 v Assembler reserves $at = $1 for its own use ² $at is called the assembler temporary register v The MARS tool has a long list of pseudo-instructions Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar slide 22
Outline v R-Type Arithmetic, Logical, and Shift Instructions v I-Type Format and Immediate Constants v Pseudo Instructions v Multiplication and Division Instructions Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar slide 23
Integer Multiplication in MIPS v Multiply instructions ² mult $s 1, $s 2 ² multu $s 1, $s 2 Signed multiplication Unsigned multiplication $0 $1 v 32 -bit multiplication produces a 64 -bit Product . . v Separate pair of 32 -bit registers ² HI = high-order 32 -bit of product ² LO = low-order 32 -bit of product v MIPS also has a special mul instruction ² mul $s 0, $s 1, $s 2 $s 0 = $s 1 × $s 2 ² Put low-order 32 bits into destination register ² HI & LO are undefined Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar slide 24 $31 Multiply Divide HI LO
Integer Division in MIPS v Divide instructions ² div $s 1, $s 2 ² divu $s 1, $s 2 Signed division Unsigned division v Division produces quotient and remainder $0 $1 v Separate pair of 32 -bit registers . . ² HI = 32 -bit remainder $31 ² LO = 32 -bit quotient Multiply ² If divisor is 0 then result is unpredictable v Moving data from HI/LO to MIPS registers ² mfhi Rd (move from HI to Rd) ² mflo Rd (move from LO to Rd) Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar slide 25 Divide HI LO
Integer Multiply/Divide Instructions Instruction multu mul divu mfhi mflo Rs, Rt Rd, Rs, Rt Rd Rd Meaning Hi, Lo = Rs × Rt Rd = Rs × Rt Hi, Lo = Rs / Rt Rd = Hi Rd = Lo Format op 6 = 0 0 x 1 c op 6 = 0 Rs 5 Rs 5 0 0 Rt 5 Rt 5 0 0 Rd 5 0 0 0 0 x 18 0 x 19 0 x 02 0 x 1 a 0 x 1 b 0 x 10 0 x 12 v Signed arithmetic: mult, div (Rs and Rt are signed) ² LO = 32 -bit low-order and HI = 32 -bit high-order of multiplication ² LO = 32 -bit quotient and HI = 32 -bit remainder of division v Unsigned arithmetic: multu, divu (Rs and Rt are unsigned) v NO arithmetic exception can occur Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar slide 26
Integer to String Conversion v Objective: convert an unsigned 32 -bit integer to a string v How to obtain the decimal digits of the number? ² Divide the number by 10, Remainder = decimal digit (0 to 9) ² Convert decimal digit into its ASCII representation ('0' to '9') ² Repeat the division until the quotient becomes zero ² Digits are computed backwards from least to most significant v Example: convert 2037 to a string ² Divide 2037/10 quotient = 203 remainder = 7 char = '7' ² Divide 203/10 quotient = 20 remainder = 3 char = '3' ² Divide 20/10 quotient = 2 remainder = 0 char = '0' ² Divide 2/10 quotient = 0 remainder = 2 char = '2' Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar slide 27
Integer to String #-------------------------------# Converts an unsigned integer into a string # Input: $a 0 = unsigned integer # In/Out: $a 1 = address of string buffer (12 bytes) #-------------------------------move li addiu sb convert: divu mflo mfhi addiu sb bnez $t 0, $a 0 $t 1, 10 $a 1, 11 $zero, 0($a 1) # # $t 0 = $t 1 = start store $t 0, $t 0 $t 2, $a 1, $t 2, $t 0, # # # # LO = quotient, HI = remainder $t 0 = quotient $t 2 = remainder convert digit to a character point to previous byte store digit character loop if quotient is not 0 Instruction Set Architecture $t 1 $t 2, 0 x 30 $a 1, -1 0($a 1) convert COE 301 – Computer Organization – KFUPM dividend = unsigned integer divisor = 10 at end of string buffer a NULL byte © Muhamed Mudawar slide 28
- Coe 301 kfupm
- Access memory
- Coe 301
- Coe 301
- Mips div
- Mudawar
- Conditional move instruction
- Coe logic
- Arithmetic overflow mips
- Daa instruction in 8051 example
- A microprogram sequencer ______________________.
- Li pseudo instruction
- Mips multiply instruction
- Mips architecture tutorial
- Li in mips
- The objective of sharpening spatial filter is to
- Arithmetic logic unit
- Arithmetic logic unit
- Computer arithmetic: algorithms and hardware designs
- Data representation and computer arithmetic
- First order logic vs propositional logic
- First order logic vs propositional logic
- Third order logic
- Concurrent vs sequential
- Cryptarithmetic problem logic+logic=prolog
- Software development wbs
- Combinational logic sequential logic
- Combinational logic sequential logic 차이
- Logic chapter three